A terminal member connected to a connection target portion includes: a bent portion bent toward the connection target portion; and a tip connection portion provided at a tip part of the bent portion, in which the tip connection portion is connected to the connection target portion via a conductive bonding material.

A semiconductor device includes: an insulating substrate; a semiconductor chip; a base plate; a first heat dissipating material; and a case. The semiconductor chip and a sealing material for sealing the semiconductor chip are housed in the case. The insulating substrate includes an insulating layer and a conductor pattern provided on an upper surface of the insulating layer. The semiconductor chip is joined onto the conductor pattern by a joining material. A lower surface of the insulating substrate and an upper surface of the base plate are in contact with each other with interposition of the first heat dissipating material. The insulating substrate and the base plate are not fixed to each other.

A semiconductor device includes: an insulating substrate; a semiconductor chip; a base plate; a first heat dissipating material; and a case. The semiconductor chip and a sealing material for sealing the semiconductor chip are housed in the case. The insulating substrate includes an insulating layer and a conductor pattern provided on an upper surface of the insulating layer. The semiconductor chip is joined onto the conductor pattern by a joining material. A lower surface of the insulating substrate and an upper surface of the base plate are in contact with each other with interposition of the first heat dissipating material. The insulating substrate and the base plate are not fixed to each other.

An electronics assembly includes a plurality of planar conductive metal sheets including a first conductive metal sheet, a second conductive metal sheet attached and electrically coupled to the first metal sheet, and a third conductive metal sheet attached and electrically coupled to the second metal sheet. The second metal sheet is located between the first and third conductive metal sheets. Air gaps are defined in the plurality of planar conductive metal sheets to form metal traces that define electrically isolated conductive paths from an outer surface of the first conductive metal sheet to an outer surface of the third conductive metal sheet in a multilevel conductive wiring network. The multilevel conductive wiring network can be attached and electrically coupled to a microchip and to one or more capacitors to form a power converter.

Disclosed is a semiconductor article including: a metal bus bar and a metal heat sink wherein at least a portion of a first side of the metal bus bar is bonded to at least a portion of the metal heat sink by a polyimide layer without adhesive; and a semiconductor power device disposed on a second side of the metal bus bar.

Disclosed is a semiconductor article including: a metal bus bar and a metal heat sink wherein at least a portion of a first side of the metal bus bar is bonded to at least a portion of the metal heat sink by a polyimide layer without adhesive; and a semiconductor power device disposed on a second side of the metal bus bar.

A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern on an upper surface of the insulating plate and a heat dissipating plate on a lower surface of the insulating plate. The module further includes a semiconductor device having upper and lower surfaces, and including a collector electrode on the device upper surface, an emitter electrode and a gate electrode on the device lower surface, and the emitter electrode and the gate electrode each being bonded to an upper surface of the circuit pattern via a bump, and a block electrode bonded to the collector electrode. The block electrode includes a flat plate portion covering over the semiconductor device, and a pair of projecting portions projecting toward the circuit pattern from both ends of the flat plate portion in a thickness direction orthogonal to a surface of the insulating plate, and being bonded to the circuit pattern.

A semiconductor sub-assembly and a semiconductor power module capable of having the reduced thickness of a chip and reduced thermal resistance are provided. The semiconductor sub-assembly includes a single or a plurality of semiconductor chips having a first electrode that is formed on the lower surface thereof, a second electrode that is formed on the upper surface thereof, and a plurality of chip-side signal electrode pads that are formed at one end of the upper surface thereof. The semiconductor chip is embedded in the embedded structure and a plurality of extension signal electrode pads are connected to each of the chip-side signal electrode pads. The extension signal electrode pad is formed on the embedded substrate in a size greater than the chip-side signal electrode pad when viewed on the plane.

A method of manufacturing a module is disclosed. In one example, the method comprises providing at least one solder body with a base portion and an elevated edge extending along at least part of a circumference of the base portion. At least one carrier, on which at least one electronic component is mounted, is placed in the at least one solder body so that the at least one carrier is positioned on the base portion and is spatially confined by the elevated edge.

Implementations of semiconductor devices may include a die coupled over a lead frame, a redistribution layer (RDL) coupled over the die, a first plurality of vias coupled between the RDL and the die, and a second plurality of vias coupled over and directly to the lead frame. The second plurality of vias may be adjacent to an outer edge of the semiconductor device and may be electrically isolated from the die.