A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. A plurality of conductive balls is placed over a circuit substrate, where each of the conductive balls is placed over a contact area of one of a plurality of contact pads that is accessibly revealed by a patterned mask layer. The conductive balls are reflowed to form a plurality of external terminals with varying heights connected to the contact pads of the circuit substrate, where a first external terminal of the external terminals formed in a first region of the circuit substrate and a second external terminal of the external terminals formed in a second region of the circuit substrate are non-coplanar.

Provided is a package-on-package (PoP). The PoP includes a lower package, an upper package on the lower package, an interposer substrate disposed between the lower package and the upper package, and a plurality of balls connecting the interposer substrate to the upper package, in which the lower package includes a first substrate, and a first die and a second die disposed side by side in a horizontal direction, on the first substrate, in which the upper package includes a second substrate, a third die on the second substrate, and a plurality of ball pads disposed on a surface of the second substrate, the interposer substrate comprises on a surface thereof a plurality of ball lands to which a plurality of balls are attached, and at least some of the plurality of ball lands overlap the first die and the second die in a vertical direction that intersects the horizontal direction.

Provided is a fan-out semiconductor package including a package body having a fan-in region and a fan-out region, the fan-out region surrounding the fan-in region and including a body wiring structure; a fan-in chip structure in the fan-in region, the fan-in chip structure comprising a chip and a chip wiring structure on a top surface of the chip; a first redistribution structure on a bottom surface of the package body and a bottom surface of the fan-in chip structure, the first redistribution structure comprising first redistribution elements extending towards the fan-out region; and a second redistribution structure on a top surface of the package body and a top surface of the chip wiring structure, the second redistribution structure comprising second redistribution elements extending towards the fan-out region.

A package structure is provided. The package structure includes a semiconductor die and a thermoelectric structure disposed on the semiconductor die. The thermoelectric structure includes P-type semiconductor blocks, N-type semiconductor blocks and metal pads. The P-type semiconductor blocks and the N-type semiconductor blocks are arranged in alternation with the metal pads connecting the P-type semiconductor blocks and the N-type semiconductor blocks. When a current flowing through one of the N-type semiconductor block, one of the metal pad, and one of the P-type semiconductor block in order, the metal pad between the N-type semiconductor block and the P-type semiconductor block forms a cold junction which absorbs heat generated by the semiconductor die.

An electronic device is disclosed and includes a conductive layer, a first dielectric layer, and a second dielectric layer, in which the second dielectric layer is disposed on the first dielectric layer, the conductive layer is disposed between the first dielectric layer and the second dielectric layer, the first dielectric layer has a first transmittance for a light, the second dielectric layer has a second transmittance for the light, and the first transmittance is different from the second transmittance.

The invention discloses a semiconductor package structure including a package carrier, at least one electronic component, a packaging layer, a support component and a shielding layer. The electronic component is disposed on a first surface of the package carrier. The packaging layer is disposed on the first surface and covers the electronic component. The support component is embedded in the packaging layer to surround the electronic component. An end surface of the support component is electrically connected to a build-up circuit and electrically grounded. A patterned metal layer of the shielding layer is electrically connected to the support component. The shielding range of the patterned metal layer covers at least electronic component. A shielding space, which covers the electronic component, is formed by the support component and the shielding layer. In addition, a semiconductor EMI shielding component and a method of making a semiconductor package structure are also disclosed.

An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area has interconnects that provide electrical accesses to display elements on the display area. A driver chip is disposed on the driver area and includes a first edge adjacent to the display area, two side edges connected to the first edge, and a plurality of pad groups. Each pad group includes a row of electronic pads that are electrically coupled to a subset of display elements via a subset of interconnects routed on the fan-out area. The pad groups include a first pad group and a second pad group disposed immediately adjacent to the first pad group. A first subset of interconnects cross one of the two side edges, and extend above a gap between rows of the first and second pad groups to reach the first pad group.

A semiconductor package includes: a first wiring structure including a first wiring layer, and a second wiring layer disposed on the first wiring layer, and connected to a first connecting structure placed disposed on the first wiring layer; a first semiconductor chip disposed on the first wiring structure and connected to the first wiring structure through a first connecting pad disposed on a first side of the first semiconductor chip; a second wiring structure disposed on the first semiconductor chip; and an insulating member disposed between the first and second wiring structures, wherein the first wiring structure further includes a first signal pattern that is electrically connected to the first connecting pad, and the first signal pattern redistributes the first connecting pad to the first connecting structure via the insulating member.

A semiconductor package includes a package substrate, a semiconductor stack on the package substrate, a passive device on the package substrate and spaced apart from the semiconductor stack, and a stiffener on the package substrate and extending around an outer side of the semiconductor stack. The stiffener includes a first step surface extends over the passive device. A width of a bottom surface of the stiffener is smaller than a width of a top surface of the stiffener.

Provided is a semiconductor package including a first semiconductor chip provided on a package substrate, an interconnection substrate provided on the package substrate, the interconnection substrate having a side surface facing the first semiconductor chip, and a second semiconductor chip provided on the interconnection substrate and extended to a region on a top surface of the first semiconductor chip, wherein the interconnection substrate includes a lower interconnection layer facing the package substrate, an upper interconnection layer facing the first semiconductor chip, and a passive device between the lower interconnection layer and the upper interconnection layer, and wherein the passive device is electrically connected to the second semiconductor chip.