A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first magnetic element and a second magnetic element over the semiconductor substrate. The semiconductor device structure also includes a first conductive line extending exceeding an edge of the first magnetic element. The semiconductor device structure further includes a second conductive line extending exceeding an edge of the second magnetic element. The second conductive line is electrically connected to the first conductive line.

A substrate embedded electronic component package includes a core member having a cavity in which a metal layer is disposed on a bottom surface thereof, an electronic component disposed in the cavity, an encapsulant filling at least a portion of the cavity and covering at least a portion of each of the core member and the electronic component, and a connection structure disposed on the encapsulant and including a first wiring layer connected to the electronic component. A wall surface of the cavity has at least one groove portion protruding outwardly from a center of the cavity, and the groove portion extends to a same depth in the core member as a depth of the cavity.

A semiconductor package is provided. The semiconductor package includes a first die and a second die bonded to the first die. An encapsulant laterally encapsulates the second die. Through vias are disposed in the encapsulant. An interconnect structure is disposed on the second die, the through vias and the encapsulant. A redistribution structure is disposed on the interconnect structure. An inductor is embedded in the redistribution structure and the interconnect structure, wherein the inductor includes a portion of a metallization pattern of the redistribution structure and a portion of a conductive pattern of the interconnect structure. The portion of the metallization pattern of the inductor is adjacent to and substantially overlapped with the portion of the conductive pattern of the inductor. A manufacturing method of a semiconductor package is also provided.

A protection device includes a first inductive element connecting first and second terminals and a second inductive element connecting third and fourth terminals. A first component includes a first avalanche diode connected in parallel with a first diode string, anodes of the first avalanche diode and a last diode in the string being connected to ground, cathodes of the first avalanche diode and a first diode in the string being connected, and a tap of the first diode string being connected to the first terminal. A second protection component includes a second avalanche diode connected in parallel with a second diode string, anodes of the second avalanche diode and a last diode in the string being connected to ground, cathodes of the second avalanche diode and a first diode in the string being connected, and a tap of the second diode string being connected to the third terminal.

A semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; and a magnetic core in the second passivation layer, wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a high resistance isolation layer, and the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm.

A filter structure includes a ground plane in a first metal layer of an integrated circuit (IC) package, a plate in a second metal layer of the IC package, a dielectric layer between the ground plane and the plate, the ground plane, the dielectric layer, and the plate thereby being configured as a capacitive device, and an inductive device in a third metal layer of the IC package. The inductive device is electrically connected to the plate, and the plate and the inductive device are configured to have a resonance frequency greater than 1 GHz.

An integrated circuit includes a semiconductor substrate and a metallization structure over the semiconductor substrate. The metallization structure includes: a dielectric layer having a surface; a conductive routing structure; and an electronic circuit. Over the surface of the dielectric layer, a material is configured to set or adjust the electronic circuit.

The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

A semiconductor device includes a first semiconductor chip in which a first multilayer wiring structure including a first coil and a second coil is formed and a second semiconductor chip in which a second multilayer wiring structure including a third coil and a fourth coil is formed. The second semiconductor chip is joined to the first semiconductor chip such that the first coil (second coil) and the third coil (fourth coil) are overlapped and the second semiconductor chip does not have an offset structure with respect to the first semiconductor chip. The second semiconductor chip is joined to the first semiconductor chip such that it is not overlapped with a pad for the first semiconductor chip and a pad for the second semiconductor chip.

An inductor includes a semiconductor substrate provided with a plurality of wiring levels including a first wiring level and a second wiring level, a straight conductive line, at the first wiring level of the semiconductor substrate, having a first end, a conductive coil of a spiral pattern, at the second wiring level over the first wiring level, having a second end, and a conductive via vertically connecting the first end of the straight conductive line to the second end of the conductive coil. When viewed in a plan view, a plurality of dummy patterns are arranged in a first area defined by an innermost turn of the spiral pattern.