The invention pertains to the technical field of semiconductor devices, and specifically relates to a three-dimensional capacitor-inductor based on a high-functional-density through silicon via structure and a manufacturing method. The three-dimensional capacitor-inductor of the present invention includes: a substrate formed with a through silicon via; a three-dimensional capacitor, formed on a sidewall of the through silicon via, and sequentially including a first metal layer, a second insulating layer, and a second metal layer; and a three-dimensional inductor, composed of center-filled metal of the through silicon via and planar thick metal rewiring, wherein a first insulating layer is provided between the sidewall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is provided between the three-dimensional capacitor and the three-dimensional inductor. The invention can effectively increase the values of capacitance and inductance in an integrated system, and at the same time can integrate capacitors and inductors near the chip in three-dimensional integration, and can also improve the functional density of through silicon via in three-dimensional integration and increase the utilization rate of silicon in system integration. Compared with discrete capacitors and inductors on other organic substrates, the integration can be greatly improved.

A multilayer wiring structure in which a plurality of conductive films and a plurality of interlayer dielectric films are laminated is formed so as to cover a main surface of a first semiconductor chip. The conductive films include conductive films to which a low voltage is applied and conductive films to which a high voltage is applied. The conductive films to which the low voltage is applied are located below the conductive films to which the high voltage is applied and closer to the main surface of a semiconductor substrate. The conductive films are arranged as conductive films of at least one layer between a first inductor to which the low voltage is applied and a second inductor to which the high voltage is applied.

An integrated circuit structure comprises one or more sets of first and second conductive lines along a same direction in an interlayer dielectric (ILD), the first and second conductive lines having a width greater than 2 μm. An air gap is in the ILD between the first and second conductive lines, the air gap extending across the ILD to sidewalls of the first and second conductive lines.

A semiconductor package includes a first die, a second die, an encapsulant, a first inductor and a second inductor. The second die is stacked on the first die along a first direction. The encapsulant encapsulates the second die over the first die. The first inductor is disposed in the encapsulant and has a first spiral structure, wherein the first spiral structure has a plurality of first coils around a first axis, and the first axis is substantially perpendicular to the first direction. The second inductor is disposed in the encapsulant and having a second spiral structure, wherein the first inductor and the second inductor are disposed at opposite sides of the second die.

A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric layer, a first spiral trace layer disposed in the insulating redistribution layer, and a second spiral trace layer disposed in the inter-metal dielectric layer and correspondingly formed below the first spiral trace layer. The inter-metal dielectric layer has a separating region to divide the second spiral trace layer into line segments. First slit openings each passes through a corresponding line segment, and extends in an extending direction of a length of the corresponding line segment.

A tunable inductor arrangeable on a chip or substrate comprises a first winding part connected at one end to a first input of the tunable inductor arrangement, a second winding part connected at one end to the other end of the first winding part, a third winding part connected at one end to a second input of the tunable inductor arrangement, a fourth winding part connected at one end to the other end of the third winding part, and a switch arrangement arranged. The switch arrangement tunes the tunable inductor by selectively connecting the first and fourth winding parts in parallel and the second and third winding parts in parallel, with the parallel couplings in series between the first and second inputs, or connecting the first, second, fourth and third winding parts in series between the first and second inputs. Corresponding transceivers, communication devices, methods and computer programs are disclosed.

A semiconductor package structure includes a plurality of transducer devices, a cap structure, at least one redistribution layer (RDL) and a protection material. The transducer devices are disposed side by side. Each of the transducer devices has at least one transducing region, and includes a die body and at least one transducing element. The die body has a first surface and a second surface opposite to the first surface. The transducing region is disposed adjacent to the first surface of the die body. The transducing element is disposed adjacent to the first surface of the die body and within the transducing region. The cap structure covers the transducing region of the transducer device to form an enclosed space. The redistribution layer (RDL) electrically connects the transducer devices. The protection material covers the transducer devices.

An inductor includes a first metallization layer multi-turn trace. The inductor also includes a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via. The inductor further includes a plurality of discrete third metallization layer trace segments coupled to the second metallization layer multi-turn trace through a plurality of second vias.

A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.

An integrated circuit structure comprises one or more first level interconnects (FLIs) embedded in an underfill (UF) over a substrate. An etch stop layer is over the FLIs. A passivation layer is over the etch stop layer and a plurality of vias are through the passivation layer. A plurality of contacts are on the passivation layer in contact with the vias to connect with the FLI. A plurality of topological crack stop (TCS) features are formed in the passivation layer and on a top surface of the etch stop layer.