In one embodiment, a first die comprises: a first die-to-die adapter to communicate with first protocol layer circuitry via a flit-aware die-to-die interface (FDI) and first physical layer circuitry via a raw die-to-die interface (RDI), where the first die-to-die adapter is to receive message information comprising first information of a first interconnect protocol; and the first physical layer circuitry coupled to the first die-to-die adapter. The first physical layer circuitry may be configured to receive and output the first information to a second die via an interconnect, the first physical layer circuitry comprising a plurality of modules, each of the plurality of modules comprising an analog front end having transmitter circuitry and receiver circuitry. Other embodiments are described and claimed.

Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via. Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

A semiconductor module is provided that includes a low side switch, a high side switch and a control chip. The low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit. The switch node connector includes two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area. The arrangement and the cross-sectional area of the two or more branches are selected so as to homogenise the current density distribution within the switch node connector.

A microelectronic device comprises a stack structure comprising blocks separated from one another by dielectric slot structures. At least one of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction. A filled trench vertically overlies and is within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench comprises a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions, and dielectric structures on and having a different material composition than the dielectric liner material. The dielectric structures are substantially confined within horizontal areas of the steps of the stadium structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

A structure including a first die, a second die, a first insulating encapsulant, an interconnection die, and a second insulating encapsulant is provided. The first die includes a first bonding structure. The first bonding structure includes a first dielectric layer and a first conductive pad embedded in the first dielectric layer. The second die includes a second bonding structure. The second bonding structure includes a second dielectric layer and a second conductive pad embedded in the second dielectric layer. The first insulating encapsulant laterally encapsulates the first die and the second die. The interconnection die includes a third bonding structure. The third bonding structure includes a third dielectric layer and third conductive pads embedded in the third dielectric layer. The second insulating encapsulant laterally encapsulates the interconnection die. The third bonding structure is in contact with the first bonding structure and the second bonding structure.

A power semiconductor module includes a semiconductor board and a number of semiconductor chips attached to the semiconductor board. Each semiconductor chip has two power electrodes. An adapter board is attached to the semiconductor board above the semiconductor chips. The adapter board includes a terminal area for each semiconductor chip on a side facing away from the semiconductor board. The adapter board, in each terminal area, provides a power terminal for each power electrode of the semiconductor chip associated with the terminal area. Each power terminal is electrically connected via a respective vertical post below the terminal area with a respective semiconductor chip and each of the power terminals has at least two plug connectors. Jumper connectors interconnect the plug connectors for electrically connecting power electrodes of different semiconductor chips.

A semiconductor package includes a frame having a first surface and a second surface, and including a wiring structure and a through-hole. The package further includes a first redistribution structure disposed on the first surface of the frame and including a first insulating layer and a first redistribution layer on the first insulating layer and connected to the wiring structure, a bridge die in the through-hole and having an interconnector, and an encapsulant surrounding the bridge die, and covering the second surface of the frame. The package further includes a second redistribution structure disposed on the encapsulant, and including a second insulating layer and a second redistribution layer on the second insulating layer and connected to the interconnector and the wiring structure, and a plurality of semiconductor chips disposed on the second redistribution structure, connected to the second redistribution layer, and electrically connected to each other through the interconnector.

A package comprising a substrate, an integrated device, and an interconnect integrated device. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects. The integrated device is coupled to the substrate. The interconnect integrated device is coupled to a surface of the substrate. The integrated device, the interconnect integrated device and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, that travels through at least the substrate, then through the interconnect integrated device and back through the substrate.

A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.