Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.

A power module includes a number of sub-modules connected via removable jumpers. The removable jumpers allow the connections between one or more power semiconductor die in the sub-modules to be reconfigured, such that when the removable jumpers are provided, the power module has a first function, and when the removable jumpers are removed, the power module has a second function. The removable jumpers may also allow for independent testing of the sub-modules. The power module may also include a multi-layer printed circuit board (PCB), which is used to connect one or more contacts of the power semiconductor die. The multi-layer PCB reduces stray inductance between the contacts and therefore improves the performance of the power module.

An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface.

A semiconductor device includes a first chip package, a heat dissipation structure and an adapter. The first chip package includes a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die has an active surface and a back surface opposite to the active surface. The heat dissipation structure is connected to the chip package. The adapter is disposed over the first chip package and electrically connected to the semiconductor die.

A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.

A multi-chip packaged device may include a first integrated circuit die with a first integrated circuit, such that the first integrated circuit may include a first plurality of ports disposed on a first side and a second plurality of ports disposed on a second side of the first integrated circuit die. The multi-chip packaged device may also include a second integrated circuit die, such that the second integrated circuit may include a third plurality of ports disposed on a third side of the second integrated circuit die. The first integrated circuit may communicate with the first side of the second integrated circuit when placed adjacent to the first side and communicate with the second side of the first integrated circuit die when placed adjacent to the second side.

A method includes detecting an open in a first IO element of a first bank of IOs and not in a second bank of IOs. The first and second banks of IOs are in a channel of a first die. The method includes shifting a first connection between the first IO element and a first core fabric of the first die to second connection between a second IO element and the first core fabric. The second IO element is in the first bank of IOs. The method includes shifting a third connection between a third IO element and a second core fabric of a second die to fourth connection between a fourth IO element and the second core fabric. The third and fourth IO elements are in a third bank of IOs of the second die. The method includes not shifting connections in the second and fourth banks of IOs.

A semiconductor package includes a processor, a lower memory including a plurality of lower memory chips that are vertically stacked, an interposer mounted on the processor and the lower memory, and an upper memory mounted on the interposer, the upper memory including a plurality of upper memory chips that are vertically stacked. The interposer includes a first physical layer (PHY) transmitting and receiving a signal between the processor and the lower memory and transmitting and receiving a signal between the processor and the upper memory, and the processor includes a second PHY communicating with the first PHY and a first through silicon via (TSV) electrically connecting the first PHY to the second PHY.

Methods for creating a conductive feature in a dielectric material are provided. In an embodiment, such a method comprises irradiating a region of a dielectric material having a resistivity of at least 10.sup.8 W cm with a focused ion beam, the irradiated region corresponding to a conductive feature embedded in the dielectric material, the conductive feature having a conductivity greater than that of the dielectric material; and forming one or more contact pads of a conductive material in electrical communication with the conductive feature, the one or more contact pads configured to apply a voltage across the conductive feature using a voltage source.

A composite component that includes an interposer structure and an electronic component. The interposer structure includes a Si base layer having a first main surface and a second main surface facing each other, a rewiring layer on the first main surface, a through Si via electrically connected to the rewiring layer and penetrating the Si base layer, an interposer electrode facing the second main surface, and an adhesive layer. The electronic component has a surface and a component electrode on the surface and connected to the through Si via, and is located between the interposer electrode and the Si base layer such that the component electrode and the surface are adhered to the second main surface of the Si base layer with the adhesive layer interposed therebetween. The through Si via extends from the second main surface, penetrates the adhesive layer, and is electrically connected to the component electrode.