A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.

The invention relates to a multi-layer 3D foil package and to a method for manufacturing such a multi-layer 3D foil package. The 3D foil package has a foil substrate stack having at least two foil planes, wherein a first electrically insulating foil substrate is arranged in a first foil plane, and wherein a second electrically insulating foil substrate is arranged in a second foil plane, wherein the first foil substrate has a first main surface region on which at least one functional electronic component is arranged, wherein the second foil substrate has a cavity having at least one opening in the second main surface region, wherein the foil substrates within the foil substrate stack are arranged one above the other such that the functional electronic component arranged on the first foil substrate is arranged within the cavity provided in the second foil substrate.

A semiconductor device includes a circuit substrate, a semiconductor package, connective terminals and supports. The circuit substrate has a first side and a second side opposite to the first side. The semiconductor package is connected to the first side of the circuit substrate. The connective terminals are located on the second side of the circuit substrate and are electrically connected to the semiconductor package via the circuit substrate. The supports are located on the second side of the circuit substrate beside the connective terminals. A material of the supports has a melting temperature higher than a melting temperature of the connective terminals.

The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

Semiconductor devices having electrical interconnections through vertically stacked semiconductor dies, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die can include surfaces having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. The semiconductor dies can be directly coupled to each other via the insulating material. The semiconductor assembly can further include an interconnect structure electrically coupled to each of the semiconductor dies. The interconnect structure can include a monolithic via extending continuously through each of the semiconductor dies in the die stack. The interconnect structure can also include a plurality of protrusions extending from the monolithic via. Each protrusion can be positioned within the recess of a respective semiconductor die and can be electrically coupled to the conductive pad within the recess.

In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.

Embodiments may relate an electronic device that includes a first platform and a second platform coupled with a chassis. The platforms may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first platform and the second platform such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.

A semiconductor package includes a first semiconductor chip mounted on the package substrate, a second semiconductor mounted on the package substrate and set apart from the first semiconductor chip in a horizontal direction thereby forming a gap between the first semiconductor chip and the second semiconductor chip. The semiconductor package further includes a first thermal interface material layer formed in the gap and having a first modulus of elasticity and a second thermal interface material layer formed on each of the first semiconductor chip and the second semiconductor chip and having a second modulus of elasticity, wherein the first modulus of elasticity is less than the second modulus of elasticity.

A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

A die dipping structure includes a plate including a first recessed portion having a first depth and filled with a first flux material. The plate further includes a second recessed portion, isolated from the first recessed portion, with a second depth and filled with a second flux material. The second depth is different from the first depth. The die dipping structure further includes a motor configured to move the plate so as to simultaneously dip a first die and a second die into the flux of the first recessed portion and the flux of the second recessed portion, respectively.