A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided.

A semiconductor package includes a first semiconductor chip including a first surface and a second surface, and including a first active layer on a portion adjacent to the first surface; a first redistribution structure on the first surface of the first semiconductor chip, wherein the first redistribution structure includes a first area and a second area next to the first area; a second semiconductor chip mounted in the first area of the first redistribution structure, including a third surface, which faces the first surface, and a fourth surface, and including a second active layer on a portion adjacent to the third surface; a conductive post mounted in the second area of the first redistribution structure; a molding layer at least partially surrounding the second semiconductor chip and the conductive post on the first redistribution structure; and a second redistribution structure disposed on the molding layer and connected to the conductive post.

A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and a first encapsulant covering at least a portion of each of the inactive surface and a side surface of the semiconductor chip. A metal layer is disposed on the first encapsulant, and includes a first conductive layer and a second conductive layer, sequentially stacked. A connection structure is disposed on the active surface of the semiconductor chip, and includes a first redistribution layer electrically connected to the connection pad. A lower surface of the first conductive layer is in contact with the first encapsulant and has first surface roughness, and an upper surface of the first conductive layer is in contact with the second conductive layer and has second surface roughness smaller than the first surface roughness.

A semiconductor structure includes a molding, a device in the molding, and a RDL over the device and the molding. The RDL includes a first portion directly over a surface of the molding, and a second portion directly over a surface of the device. A bottom surface of the first portion is in contact with the surface of the molding, and a bottom surface of the second portion is in contact with the surface of the device. The bottom surface of the first portion of the RDL and the bottom surface of the second portion of the RDL are at different levels and misaligned from each other. A thickness of the first portion is greater than a thickness of the second portion.

Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.

A package includes at least one memory component and an insulating encapsulation. The at least one memory component includes a stacked memory structure and a plurality of conductive posts. The stacked memory structure is laterally encapsulated in a molding compound. The conductive posts are disposed on an upper surface of the stacked memory structure. The upper surface of the stacked memory structure is exposed from the molding compound. The insulating encapsulation encapsulates the at least one memory component. The top surfaces of the conductive posts are exposed form the insulating encapsulation. A material of the molding compound is different a material of the insulating encapsulation.

A cyclic cooling embedded packaging substrate and a manufacturing method thereof are disclosed. The packaging substrate includes a dielectric material body, a chip, a first metal face, a second metal face and a first trace. The dielectric material body is provided with a packaging cavity, the chip is packaged in the packaging cavity, the first metal face is embedded in the dielectric material body, covers and is connected to a heat dissipation face of the chip. The second metal face is embedded in the dielectric material body, connected to a surface of the first metal face, and is provided with a first cooling channel pattern for forming a cooling channel. The first trace is arranged on a surface of the dielectric material body or embedded therein, and is connected with a corresponding terminal on an active face of the chip through a first conductive structure.

A semiconductor package includes: a first redistribution layer; a first semiconductor chip including a first side and a second side, wherein the first side faces the first redistribution layer; a first sealing material covering the second side of the first semiconductor chip and having a first filler content; a second sealing material formed on the first sealing material and having a second filler content lower than the first filler content; and a second redistribution layer disposed on the second sealing material.

A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

Certain aspects of the present disclosure generally relate to an embedded trace substrate (ETS) with one or more passive components embedded therein. Such an ETS may provide shorter routing, smaller loop area, and lower parasitics between a semiconductor die and a land-side passive component embedded in the ETS. One example embedded trace substrate generally includes a core, a first insulating material disposed above the core and having a first metal pattern embedded therein, a second insulating material disposed below the core and having a second metal pattern embedded therein, and one or more passive components embedded in the core.