Described examples include an apparatus including a package substrate having a die attach pad and a first semiconductor die on the die attach pad, the first semiconductor die including a transmitter. The apparatus also includes an assembly having a first plate coupled to the transmitter, a second plate separated from the first plate by a dielectric and a second semiconductor die on the die attach pad, the second semiconductor die including a receiver coupled to the second plate.

An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

An electrical power converter with segmented windings is provided. Comprises a transformer or autotransformer including a magnetic core (3) and at least a primary winding (51) and at least a secondary winding (52) arranged around the magnetic core (3). The primary winding and/or the secondary winding have at least one full turn that includes at least one power switch (10) and at least one capacitor (12) connected in series and arranged respectively opposite each other and facing opposite sides of the magnetic core, defining a cell (4) that is divided in four segments, a first segment (23) including said at least one switch, a second opposite segment (24) including said at least one capacitor, and two other connecting segments (21, 22) providing electrical connection between the first segment and the second segment, and each of said two other connecting segments having opposite electrical polarity.

An electronic device is provided that includes a board equipped with a pair of differential transmission lines that each have an opening extending between two line terminals. Moreover, the device includes a capacitor module that includes a support and two capacitors that each have two capacitor terminals, respectively, connected to the two line terminals of one line of the pair of transmission lines. In addition, the support includes a separating region between the two capacitors that has at least one cavity disposed between the two capacitors.

Devices, systems, and methods for serial communication over a galvanically isolated channel are disclosed. A device includes a first IC device interface, first IO components connected to the first IC device interface, a second IC device interface, second IO components connected to the second IC device interface, an insulator layer having a first major surface and a second major surface, at least one pair of capacitor plates and corresponding interconnection paths on the first major surface, and at least one pair of capacitor plates and corresponding interconnection paths on the second major surface, wherein the at least one pair of capacitor plates on the first major surface of the insulator layer are aligned with the at least one pair of capacitor plates on the second major surface of the insulator layer to form at least one pair of capacitors.

A semiconductor assembly includes a semiconductor package that includes first and second transistor dies embedded within a package body, the first and second transistor dies being arranged laterally side by side within the package body such that a first load terminal of the first transistor die faces an upper surface of the package body and such that a second load terminal of the second transistor die faces the upper surface of the package body, and a discrete capacitor mounted on the semiconductor package such that a first terminal of the discrete capacitor is directly over and electrically connected to the first load terminal of the first semiconductor die and such that a second terminal of the discrete capacitor is directly over and electrically connected with the second load terminal of the second semiconductor die.

A package structure is provided. The package structure includes a reinforced plate and multiple conductive structures penetrating through the reinforced plate. The package structure also includes a redistribution structure over the reinforced plate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The package structure further includes multiple chip structures bonded to the redistribution structure through multiple solder bumps. In addition, the package structure includes a protective layer surrounding the chip structures.

Provided are an adapter board and a method for forming the same, a packaging method, and a package structure. One form of a method for forming an adapter board includes: providing a base, including an interconnect region and a capacitor region, the base including a front surface and a rear surface that are opposite each other; etching the front surface of the base, to form a first trench in the base of the interconnect region and form a second trench in the base of the capacitor region; forming a capacitor in the second trench; etching a partial thickness of the base under the first trench, to form a conductive via; forming a via interconnect structure in the conductive via; and thinning the rear surface of the base, to expose the via interconnect structure.

An electronic package and a method for manufacturing is provided, having first and opposing second surfaces, and a circuit thereon, each of the first and second surfaces has a terminal connected to the circuit; a conductive element spaced apart from the die with top and a bottom surfaces; a body of molding compound encapsulating the die and the element, the body having a top side facing the first surface and a bottom side facing the second surface; a first package terminal at the top side connected to the terminal at the first surface, and a second package terminal at the top side connected to the top surface of the conductive element, the conductive element is formed from the first package terminal and the second package terminal; and a conductive layer connecting the bottom surface of the conductive element to the terminal arranged on the second surface of the die.

A capacitor structure including a substrate, a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, a third electrode, and a stress balance layer is provided. The substrate has trenches and a pillar portion located between two adjacent trenches. The first electrode is disposed on the substrate, on the pillar portion, and in the trenches. The first dielectric layer is disposed on the first electrode and in the trenches. The second electrode is disposed on the first dielectric layer and in the trenches. The second dielectric layer is disposed on the second electrode and in the trenches. The third electrode is disposed on the second dielectric layer and in the trenches. The third electrode has a groove, and the groove is located in the trench. The stress balance layer is disposed in the groove.