An electronic package is provided and includes an electronic element connected to a plurality of inductor circuits embedded in an insulator of a package substrate by fan-out conductive copper pillars, and at least one shielding layer non-electrically connected to the inductor circuits, where the shielding layer includes a plurality of line segments not connected to each other, such that the shielding layer shields the inductor circuits, thereby achieving the electrical requirements of high-current products while improving the inductance value and quality factor.

An inductance structure is provided and includes a plurality of inductance traces embedded in an insulating body and at least one shielding layer that is embedded in the insulating body and free from being electrically connected to the inductance traces. The shielding layer has a plurality of line segments that are free from being connected to one another. The shielding layer shields the inductance traces to improve the inductance value and quality factor.

Provided is a semiconductor device including: a circuit board; a wiring pattern; a first semiconductor chip and a second semiconductor chip; a first lead frame; and a second lead frame; wherein the first lead frame and the second lead frame each comprises: a chip joining portion provided above at least a part of the semiconductor chip; a wiring joining portion provided above at least a part of the wiring pattern; and a bridging portion for connecting the chip joining portion and the wiring joining portion; and in the first direction, a space between the bridging portion of the first lead frame and the bridging portion of the second lead frame is smaller than a space between the chip joining portion of the first lead frame and the chip joining portion of the second lead frame.

An electronic circuit having a first terminal and a second terminal. The electronic circuit includes a plurality of diodes connected in parallel, the plurality of diodes including a first diode and a second diode that respectively have applied thereto a first forward voltage and a second forward voltage, the second forward voltage being higher than the first forward voltage. A first path and a second path are formed from the first terminal, respectively via the first diode and the second diode, to the second terminal. An inductance of the first path is larger than an inductance of the second path.

Micro-scale planar-coil transformers including one or more shields are disclosed. The one or more shields can block most common-mode current from crossing from one side to another side of a transformer. Reduction of common-mode current crossing the transformer results in reduction of dipole radiation, which is the main component of electromagnetic interference (EMI) in some transformers.

A semiconductor device includes a first semiconductor element, a second semiconductor element, an insulating layer, a sealing resin, a first external terminal, a second external terminal, a first connecting conductor and a second connecting conductor. Each of the semiconductor elements has an element front surface, an element back surface, and a plurality of front surface electrodes disposed on the element front surface. The insulating layer has an insulating layer back surface facing each of the element front surfaces and an insulating layer front surface facing away from the insulating layer back surface. The sealing resin has a resin front surface in contact with the insulating layer back surface and a resin back surface facing away from the resin front surface. The sealing resin covers a portion of each semiconductor element. Each external terminal is disposed between the first and the second semiconductor elements and exposed from the resin back surface. The first connecting conductor is disposed on the insulating layer and connects at least one of the front surface electrodes of the first semiconductor element to the first external terminal. The second connecting conductor is disposed on the insulating layer and connects at least one of the front surface electrodes of the second semiconductor to the second terminal.

A power module includes at least one electrically conductive power substrate; and a plurality of power devices arranged on and connected to the at least one electrically conductive power substrate. The power module further includes at least one elevated signal element electrically connected to the plurality of power devices and/or at least one elevated power plane electrically connected to the at least one electrically conductive power substrate and electrically connected to the plurality of power devices.

A semiconductor module, including: plurality of output elements provided to constitute an upper arm and a lower arm; a resin case provided surrounding an accommodation space for accommodating the output elements; an arm-to-arm wiring line for connecting the upper arm with the lower arm; an output terminal, which is connected to the arm-to-arm wiring line and is for outputting output currents from the output elements to a load being external to the semiconductor module; a sense terminal, which is connected to the arm-to-arm wiring line and is for detecting currents that flow in the output elements; and an inductor provided between a connection point for connecting the arm-to-arm wiring line with the output terminal, and the output terminal is provided. An inductance of the inductor is 1 μH or more.

The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

An inductor includes a semiconductor substrate provided with a plurality of wiring levels including a first wiring level and a second wiring level, a straight conductive line, at the first wiring level of the semiconductor substrate, having a first end, a conductive coil of a spiral pattern, at the second wiring level over the first wiring level, having a second end, and a conductive via vertically connecting the first end of the straight conductive line to the second end of the conductive coil. When viewed in a plan view, a plurality of dummy patterns are arranged in a first area defined by an innermost turn of the spiral pattern.