A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.

A circuit including a die and an integrated passive device. The die includes a first substrate and at least one active device. The integrated passive device includes a first layer, a second substrate, a second layer and an inductance. The inductance includes vias, where the vias are implemented in the second substrate. The inductance is implemented on the first layer, the second substrate, and the second layer. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The third layer is disposed between the die and the integrated passive device. The third layer includes pillars, where the pillars respectively connect ends of the inductance to the at least one active device. The die, the integrated passive device and the third layer are disposed relative to each other to form a stack.

Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

A semiconductor structure can include: a semiconductor substrate having a first region, a second region, and an isolation region disposed between the first region and the second region; an isolation component located in the isolation region; and where the isolation component is configured to recombine first carriers flowing from the first region toward the second region, and to extract second carriers flowing from the second region toward the first region.

A semiconductor package comprises a semiconductor die and a wiring structure, which is electrically connected to the semiconductor die. Further, the semiconductor package comprises a magnetic material. The magnetic material embeds and/or encircles a portion of the wiring structure.

A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package having a first lower substrate, a first upper substrate facing the first lower substrate, and a first semiconductor chip mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package having a second lower substrate stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip mounted in an area of the second lower substrate. At least one passive element is disposed in one of the first upper substrate and the second lower substrate and electrically connected to the second semiconductor chip.

A transistor device includes a metal submount; a transistor die arranged on said metal submount; at least one integrated passive device (IPD) component that includes a substrate arranged on said metal submount; and one or more interconnects extending between the transistor die and the at least one integrated passive device (IPD) component. The substrate includes a silicon carbide (SiC) substrate.

IC devices including transformers that includes two electrically conductive layers are disclosed. An example IC device includes a transformer that includes a first coil, a second coil, and a magnetic core coupled to the two coils. The first coil includes a portion or the whole electrically conductive layers at the backside of a support structure. The second coil includes a portion or the whole electrically conductive layers at either the frontside or the backside of the support structure. The two coils may have a lateral coupling, vertical coupling, or other types of couplings. The transformer is coupled to a semiconductor device over or at least partially in the support structure. The semiconductor device may be at the frontside of the support structure. The transformer can be coupled to the semiconductor device by TSVs. The IC device may also include BPRs that facilitate backside power delivery to the semiconductor device.

A packaged electronic circuit includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer opposite the substrate, a second metal layer on the first polymer layer opposite the first metal layer, a dielectric layer on the first polymer layer and at least a portion of the second metal layer and a second polymer layer on the dielectric layer.

A power module includes a multilayer circuit board, and first and second three-phase inverters, which are mounted on the multilayer circuit board to be stacked each other. A positive-electrode-side power source conductive trace of the first three-phase inverter and a negative-electrode-side power source conductive trace of the second three-phase inverter are disposed to at least partially face each other in a stacking direction of the multilayer circuit board, such that currents respectively flow through the power source conductive traces in opposite directions in a facing section. A negative-electrode-side power source conductive trace of the first three-phase inverter and a positive-electrode-side power source conductive trace of the second three-phase inverter are disposed to at least partially face each other in the stacking direction of the multilayer circuit board), such that currents respectively flow through the power source conductive traces in opposite directions in a facing section.