According to an example embodiment of the present inventive concept, a semiconductor device includes a substrate. A first insulating layer is disposed on the substrate. A thin-film resistor is disposed in the first insulating layer. A capacitor structure is disposed on the first insulating layer and includes a first electrode pattern, a first dielectric pattern, a second electrode pattern, a second dielectric pattern and a third electrode pattern sequentially stacked. A first via is connected to the first electrode pattern and the third electrode pattern. A part of the first via is disposed in the first insulating layer. A second via is connected to the second electrode pattern, and a third via is connected to the thin-film resistor.

The present disclosure provides a power module, a chip-embedded package module and a manufacturing method of the chip-embedded package module. The chip-embedded package module includes: a chip having a first surface and a second surface that are disposed oppositely; a first plastic member including a first cover portion and a first protrusion; and a second plastic member including a second cover portion and a second protrusion. A height difference discontinuous interface structure is formed between the top surface of the second protrusion and the second surface of the chip, which cuts off a passage for expansion of delamination at an edge position of the chip, thereby effectively suppressing generation of the delamination.

A light-emitting diode display is provided. The light-emitting diode display includes a substrate, a plurality of wires, a plurality of light-emitting areas, and at least one driver IC. The plurality of wires are formed on the substrate. The plurality of light-emitting areas include a light-emitting diode area and a virtual area. The plurality of light-emitting areas are arranged in a matrix. The virtual area of the plurality of light-emitting areas corresponds to each other. The driver IC is formed on the virtual area of the plurality of the light-emitting areas or on the plurality of the light-emitting areas.

Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having a stiffener that extends beyond a package substrate outer edge, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a package substrate having a first side, a second side opposite the first side, and an outer edge extending between the first side and the second side; an IC die coupled with the first side of the package substrate, where the IC die includes a power terminal; a stiffener coupled with the first side of the package substrate, where the stiffener surrounds the IC die and includes a conductive routing region coupled with the IC die power terminal, and a passive electronic device coupled with the conductive routing region. Other embodiments may be described and/or claimed.

The present disclosure relates to semiconductor structures and, more particularly, to an ultra-high voltage resistor and methods of manufacture. The structure includes at least one resistor coupled to a well of a doped substrate, the at least one resistor being separated vertically from the well by an isolation region with one end of the resistor being attached to an input pad and another end coupled to circuitry.

A first conductive routing structure is electrically connected to a first electronic component. A second conductive routing structure is electrically connected to a second electronic component. An additive deposition process deposits a material over a surface of a processed wafer to form a conductive or resistive structure, which extends from a portion of the first conductive routing structure to a portion of the second conductive routing structure, to configure a circuit including the first and second electronic components.

Embodiments may also include a residual chemical reaction diagnostic device. The residual chemical reaction diagnostic device may include a substrate and a residual chemical reaction sensor formed on the substrate. In an embodiment, the residual chemical reaction sensor provides electrical outputs in response to the presence of residual chemical reactions. In an embodiment, the substrate is a device substrate, and the sensor is formed in a scribe line of the device substrate. In an alternative embodiment, the substrate is a process development substrate. In some embodiments, the residual chemical reaction sensor includes, a first probe pad, wherein a plurality of first arms extend out from the first probe pad, and a second probe pad, wherein a plurality of second arms extend out from the second probe pad and are interdigitated with the first arms.

Various examples provide an electronic device that includes first and second rectangular resistor segments, each resistor segment having a doped resistive region formed in a semiconductor substrate. The first resistor segment has a first trim end and a first bridge end, and the second resistor segment has a second bridge end. The first bridge end is adjacent the second bridge end. A conductive interconnect line connects to the first bridge end and to the second bridge end. At least one connection terminal to the first resistor segment is located at the first trim end.

In a method for producing semiconductor capacitors having different capacitance values on a common substrate, firstly a partially processed semiconductor substrate is produced as a semi-finished product with hole structures and filled with a layer sequence of a dielectric and an electrically conductive layerindependently of the semiconductor capacitors to be produced subsequently. The production of the semiconductor capacitors having different capacitance values only then takes place in a second production phase by corresponding metallization and structuring. The semiconductor capacitors are then separated along dividing regions through which different groups of holes are separated from one another during the production of the semi-finished product. The method enables a more cost-effective production of semiconductor capacitors having different capacitance values in small numbers of items in make-to-order fabrication (foundry process).

An integrated circuit (IC) fabricated on a Silicon-On-Insulator (SOI) wafer, having a plurality of impedance elements cascoded in series, each impedance elements having a specified value. A subset of the impedance elements are arranged to bias a first tub at a specified very high voltage (VHV) multiplied by a first predetermined ratio. A further subset of the impedance elements are arranged to bias a second tub at VHV multiplied by a second predetermined ratio and each of the impedance elements are further arranged to bias a handle and a third surrounding tub at VHV multiplied by a third predetermined ratio. A method for designing an integrated circuit using fully dielectrically isolated processes which function reliably at higher operating voltages than that provided by the conventional processes.