A packaged multichip isolation device includes leadframe including a first and second die pad, with a first and second lead extending outside a molded body having a downward extending lead bend near their outer ends. A first integrated circuit (IC) die on the first die pad has a first bond pad connected to the first lead that realizes a transmitter or receiver. A second IC die on the second die pad has a second bond pad connected to the second lead that realizes another of the transmitter and receiver. An isolation component is in a signal path of the isolation device including a capacitive isolator, or inductors for transformer isolation on or between the die. A midpoint of the thickness of the die pad is raised above a top level of the leads and in an opposite vertical direction relative to the downward extending bend of the external leads.

Provided is a semiconductor device capable of improving relative accuracy of semiconductor elements and a yield of a semiconductor integrated circuit device. The semiconductor device includes a flat region formed on a surface of a semiconductor substrate, and having an outer peripheral shape formed by regional sides and regional chamfer portions; an outer peripheral region surrounding the flat region, and having a uniform height different from a height of the flat region; a plurality of semiconductor elements having similar shapes or the same shape, and formed on the flat region; and a wiring metal connecting the plurality of semiconductor elements via contact holes formed in a second insulating film on the semiconductor elements.

An integrated circuit device is described. The integrated circuit device comprises a substrate having transmitter for receiving a signal to be transmitted to a receiver of the substrate by way of a transmission channel; a first plurality of contacts adapted to receive a first integrated circuit die, wherein a contact of the first plurality of contacts is adapted to receive the signal to be transmitted by the transmitter; a second plurality of contacts adapted to receive a second integrated circuit die, wherein a contact of the second plurality of contacts is adapted to receive the signal transmitted by the transmitter and received by the receiver; a first resistive element coupled between a contact of the first plurality of contacts and the transmitter; and a second resistive element coupled between a contact of the second plurality of contacts and the receiver. A method of transmitting data in an integrated circuit is also described.

A package for a use in a package-on-package (PoP) device and a method of forming is provided. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor.

Embodiments may also include a residual chemical reaction diagnostic device. The residual chemical reaction diagnostic device may include a substrate and a residual chemical reaction sensor formed on the substrate. In an embodiment, the residual chemical reaction sensor provides electrical outputs in response to the presence of residual chemical reactions. In an embodiment, the substrate is a device substrate, and the sensor is formed in a scribe line of the device substrate. In an alternative embodiment, the substrate is a process development substrate. In some embodiments, the residual chemical reaction sensor includes, a first probe pad, wherein a plurality of first arms extend out from the first probe pad, and a second probe pad, wherein a plurality of second arms extend out from the second probe pad and are interdigitated with the first arms.

A semiconductor package assembly includes a semiconductor package that includes a semiconductor chip bonded to a substrate. The assembly also includes a plurality of passive devices mounted on a bottom surface of the substrate opposite the semiconductor chip, the plurality of passive devices including a plurality of operable passive devices and a plurality of standoff passive devices, wherein a height of each of the plurality of standoff passive devices is greater than a height of any of the plurality of operable passive devices. The assembly also includes a plurality of solder structures attached to the bottom surface of the substrate. When mounted on a circuit board, the standoff passive devices prevent solder bridging.

A semiconductor module includes a semiconductor element, a substrate, and a bond connector designed as a gate resistor, shunt, resistor in an RC filter or fuse. The bond connector includes a core made of a first metal material and a jacket which is designed to envelope the core and made from a second metal material that is different from the first metal material, with the first metal material having an electrical conductivity which is lower than an electrical conductivity of the second metal material. At least one of the semiconductor element and the substrate is connected to the bond connector.

A semiconductor device includes a first pad defined on one surface of a first chip; a second pad defined on one surface of a second chip which is stacked on the first chip, and bonded to the first pad; a first resistor element defined in the first chip, and coupled to the first pad; and a second resistor element defined in the second chip, and coupled to the second pad.

A fabrication method for protecting an electrical component on a semiconductor device when subjected to exposure to highly energized electrons, such as those emitted during e-beam irradiation, is provided. An example method may include doping one or more lead-out regions providing an electrical connection to the electrical component of the semiconductor device. In addition, the method may further include forming the electrical component to electrically connect to at least one of the one or more lead-out regions by doping the surface of the semiconductor substrate with a second dopant. Further, the method may include forming a protective barrier on the surface of the semiconductor substrate, substantially aligned with the one or more lead-out regions. The method may further comprise creating one or more cap regions substantially covering the entire surface of the semiconductor except for the lead-out regions by doping the surface of the semiconductor with a third dopant.

In various embodiments, a passive electronic component is disclosed. The passive electronic component can have a first surface and a second surface opposite the first surface. The passive electronic component can include a nonconductive material and a capacitor embedded within the nonconductive material. The capacitor can have a first electrode, a second electrode, and a dielectric material disposed between the first and second electrodes. The first electrode can comprise a first conductive layer and a plurality of conductive fibers extending from and electrically connected to the first conductive layer. A first conductive via can extend through the passive electronic component from the first surface to the second surface, with the first conductive via electrically connected to the first electrode.