A first conductive pattern includes a first input region overlapping a first semiconductor device and a second input region overlapping a second semiconductor device. An output electrode of the first semiconductor device and an output electrode of the second semiconductor device are connected with each other by a first wiring member. The output electrode of the second semiconductor device and a second conductive pattern are connected with each other by a second wiring member. A ratio of a current flowing from the second input region to the second conductive pattern via the second semiconductor device, relative to a current flowing from the first input region to the second conductive pattern via the first semiconductor device, is equal to or greater than 0.90 and equal to or less than 1.10.

Provided are switching elements 4, gate driver ICs 5 controlling the switching elements, and substrate 1 carrying the gate driver ICs. Substrate 1 includes base 2 and conductive portion 3 with obverse and reverse surface conductive layers 31, 32. Obverse surface conductive layer 31 includes first connection portion 311 connected to control signal output terminal 51 of gate driver IC 5, second connection portion 312 connected to gate electrode 411 of switching element 4, and first wiring portion 313 interposed between first and second connection portions 311, 312. At least one obverse surface-side first electronic component 61 is provided on obverse surface of substrate 1, forming a circuit portion connecting first and second connection portions 311, 312 together with first wiring portion 313. No conductive member penetrating through base 2 in the thickness direction is connected to first wiring portion 313. These configurations increase the speed of drive control.

Packages are configured to include an electromagnetic interference (EMI) shield. According to one example, a package includes a substrate, an electrical component, and an EMI shield. The substrate includes a first surface and a second surface. The electrical component may be coupled to the first side of the substrate. The EMI shield is formed with at least one passive device. The at least one passive device is coupled to the first surface of the substrate. The at least one passive device is located laterally to the at least one electrical component, and extends along at least a portion of the electrical component. Other aspects, embodiments, and features are also included.

A noise reduction circuit is connected between at least one line of an input line and an output line of a DC-DC converter, a ground, and a ground terminal of a switching control IC included in the DC-DC converter. The noise reduction circuit includes a first capacitor connected between the at least one line and the ground terminal, a second capacitor connected between the at least one line and the ground, and an inductor connected between the ground terminal and the ground.

Provided is a semiconductor device. The semiconductor device includes a first circuit that includes a plurality of fixed resistance elements connected in series; a second circuit that includes a plurality of variable resistance elements connected in series and that is connected in series to the first circuit; a first cover portion that is provided on an upper layer side of the first circuit and that covers the first circuit; and a second cover portion that is provided on an upper layer side of the second circuit and that covers the second circuit. The first cover portion included two or more first metal films electrically connected, correspondingly, to units having any number of the fixed resistance elements, and the second cover portion includes a second metal film electrically connected to the plurality of the variable resistance elements.

A packaged multichip isolation device includes leadframe including a first and second die pad, with a first and second lead extending outside a molded body having a downward extending lead bend near their outer ends. A first integrated circuit (IC) die on the first die pad has a first bond pad connected to the first lead that realizes a transmitter or receiver. A second IC die on the second die pad has a second bond pad connected to the second lead that realizes another of the transmitter and receiver. An isolation component is in a signal path of the isolation device including a capacitive isolator, or inductors for transformer isolation on or between the die. A midpoint of the thickness of the die pad is raised above a top level of the leads and in an opposite vertical direction relative to the downward extending bend of the external leads.

An IC package includes a heat-generating device and an electrical device on a surface of a substrate, a mold compound disposed on the electrical device, and a thermal structure disposed on the heat-generating device, without the mold compound, to improve heat dissipation. In an example, the thermal structure includes a thermal interface material (TIM) layer and a heat sink. In the example, the TIM layer extends from the heat-generating device to a height equal to or less than the mold compound and the heat sink includes a planar exterior surface above the heat-generating device and the electrical device. In an example, a first heat sink portion of the heat sink on the heat-generating device may be a different thickness than a second heat sink portion of the heat sink on the electrical device. The thermal structure reduces a thermal resistance between the heat-generating device and the heat sink.

A packaged multichip isolation device includes leadframe including a first and second die pad, with a first and second lead extending outside a molded body having a downward extending lead bend near their outer ends. A first integrated circuit (IC) die on the first die pad has a first bond pad connected to the first lead that realizes a transmitter or receiver. A second IC die on the second die pad has a second bond pad connected to the second lead that realizes another of the transmitter and receiver. An isolation component is in a signal path of the isolation device including a capacitive isolator, or inductors for transformer isolation on or between the die. A midpoint of the thickness of the die pad is raised above a top level of the leads and in an opposite vertical direction relative to the downward extending bend of the external leads.

A semiconductor apparatus includes a mounting board, a system on chip (SOC) package and a memory package which are provided on the mounting board. The SOC package includes a semiconductor chip and a package substrate on which the semiconductor chip is mounted. The semiconductor apparatus further includes a signal wiring line through which a signal between the semiconductor chip and the memory package is transmitted, being provided on the package substrate and in the mounting board and a measurement terminal connected to the signal wiring line on main surface of the package substrate.

An object is to provide a power semiconductor module having a small ON-resistance and capable of operating at a high frequency. Included are: a semiconductor chip 2 configured to supply a power source, and including a voltage-driven switching element, and a gate electrode 20G provided on a main surface of the semiconductor chip 2; a heat dissipation sheet 3 disposed opposite the main surface of the semiconductor chip 2, and configured to dissipate heat of the semiconductor chip 2; a wiring board 4 disposed between the semiconductor chip 2 and the heat dissipation sheet 3, and including a gate wiring pattern 40G connected to an external terminal 6G; an interposer 5 including a sheet-like base material disposed between the semiconductor chip 2 and the wiring board 4, and a gate resistor 50G in the sheet-like base material and interposed between the gate electrode 20G and the gate wiring pattern 40G; and a resin housing 7 that seals the semiconductor chip 2, the wiring board 4, and the interposer 5.