A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.

A radar monolithic microwave integrated circuit (MMIC) includes a first transmission channel configured to output a first continuous-wave transmit signal based on a local oscillator signal having a first frequency; a first phase shifter provided on the first transmission channel and configured to apply a first phase setting to the first continuous-wave transmit signal to generate a first transmit signal having the first frequency; a first transmit monitoring signal path configured to couple out a portion of the first transmit signal from the first transmission channel as a first transmit monitoring signal; a frequency multiplier configured to receive a test signal and convert it into a multiplied test signal having a second frequency, where the first and the second frequencies are separated by a frequency offset; and a down-conversion mixer configured to mix the multiplied test signal and the first transmit monitoring signal to generate a first mixer output signal.

A radar monolithic microwave integrated circuit (MMIC) includes a first transmission channel configured to output a first continuous-wave transmit signal based on a local oscillator signal having a first frequency; a first phase shifter provided on the first transmission channel and configured to apply a first phase setting to the first continuous-wave transmit signal to generate a first transmit signal having the first frequency; a first transmit monitoring signal path configured to couple out a portion of the first transmit signal from the first transmission channel as a first transmit monitoring signal; a frequency multiplier configured to receive a test signal and convert it into a multiplied test signal having a second frequency, where the first and the second frequencies are separated by a frequency offset; and a down-conversion mixer configured to mix the multiplied test signal and the first transmit monitoring signal to generate a first mixer output signal.

A semiconductor device package includes a substrate and a shielding layer. The substrate has a first surface, a second surface opposite to the first surface and a first lateral surface extending between the first surface and the second surface. The substrate has an antenna pattern disposed closer to the second surface than the first surface. The shielding layer extends from the first surface toward the second surface of the substrate. The shielding layer covers a first portion of the first lateral surface adjacent to the first surface of the substrate. The shielding layer exposes a second portion of the first lateral surface adjacent to the second surface of the substrate.

A semiconductor device package includes a substrate and a shielding layer. The substrate has a first surface, a second surface opposite to the first surface and a first lateral surface extending between the first surface and the second surface. The substrate has an antenna pattern disposed closer to the second surface than the first surface. The shielding layer extends from the first surface toward the second surface of the substrate. The shielding layer covers a first portion of the first lateral surface adjacent to the first surface of the substrate. The shielding layer exposes a second portion of the first lateral surface adjacent to the second surface of the substrate.

A method of manufacture and structure for a monolithic single chip single crystal device. The method can include forming a first single crystal epitaxial layer overlying the substrate and forming one or more second single crystal epitaxial layers overlying the first single crystal epitaxial layer. The first single crystal epitaxial layer and the one or more second single crystal epitaxial layers can be processed to form one or more active or passive device components. Through this process, the resulting device includes a monolithic epitaxial stack integrating multiple circuit functions.

A battery system has a battery cell including a can, and a ceramic substrate, including a patterned metallized surface, mounted to the can via a thermally conductive adhesive. The battery system also has a monolithic integrated circuit that measures and transmits data about the cell mounted to the patterned metallized surface such that the ceramic substrate and monolithic integrated circuit are electrically isolated from one another.

A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.

A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.

Embodiments may relate to a multi-chip microelectronic package that includes a first die and a second die coupled to a package substrate. The first and second dies may have respective radiative elements that are communicatively coupled with one another such that they may communicate via an electromagnetic signal with a frequency at or above approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.