A display panel includes a substrate including a display area and a pad area spaced apart from the display area, and an uneven pad disposed on the substrate in the pad area. The uneven pad includes a first conductive layer, a first organic layer disposed on the first conductive layer and having an upper surface having an uneven shape, and a second conductive layer disposed on the first organic layer.

A package comprising a first integrated device comprising a first plurality of under bump metallization interconnects; a second integrated device comprising a second plurality of under bump metallization interconnects; a bridge coupled to the first integrated device and the second integrated device; an encapsulation layer at least partially encapsulating the first integrated device, the second integrated device, and the bridge; a metallization portion located over the first integrated device, the second integrated device, the bridge and the encapsulation layer, where the metallization portion includes at least one dielectric layer and a plurality of metallization interconnects; a first plurality of pillar interconnects coupled to the first plurality of under bump metallization interconnects, the first plurality of interconnects located in the encapsulation layer; and a second plurality of pillar interconnects coupled to the second plurality of under bump metallization interconnects, the second plurality of pillar interconnects located in the encapsulation layer.

A method of producing a layer stack includes a) forming a first layer having a first material composition on a substrate, b) performing intermediate processing of the substrate with the first layer, c) forming an additional layer having a second material composition, the first material composition and the second material composition differing from each other by at most 10% by weight, at least locally directly on the first layer and d) applying a second layer at least in places directly onto the additional layer.

A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects includes a first pillar interconnect comprising a first cavity. The plurality of solder interconnects comprises a first solder interconnect located in the first cavity of the first pillar interconnect. A planar cross section that extends through the first cavity of the first pillar interconnect may comprise an O shape. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width; and a second pillar interconnect portion comprising a second width that is different than the first width.

There is a problem that an area of a principal current cell is reduced by an area of a bonding pad wiring layer for a sub-cell. A source electrode 9b of a current detection cell 22 is electrically connected to a bonding pad wiring layer 12 formed on an interlayer insulating film 10 via a wiring layer contact 11. The bonding pad wiring layer 12 is formed with respect to a source electrode 9a of a principal current cell 21 so as to cover a part of the source electrode 9a via the interlayer insulating film 10. As a result, the source electrode 9b is miniaturized, and a size of the source electrode 9b is made substantially equal to a size of the current detection cell 22. Therefore, the current detection cell 22 and the principal current cell 21 are disposed close to each other.

A cryogenic under bump metallization (UBM) stack includes an adhesion and barrier layer and a conductive pillar on the adhesion and barrier layer. The conductive pillar functions as a solder wetting layer of the UBM stack and has a thickness. An indium superconducting solder bump is on the conductive pillar. The thickness of the conductive pillar is sufficient to prevent intermetallic regions, which form in the conductive pillar at room temperature due to interdiffusion, from extending through the entire thickness of the conductive pillar to maintain the structural integrity of the UBM stack. The indium (In) solder bump may be formed through electroplating, with the conductive pillar being copper (Cu) and the adhesion and barrier layer being titanium tungsten (TiW) and a thin seed layer of copper (Cu), or a layer of titanium (Ti). The UBM stack eliminates the need for magnetic materials such as nickel (Ni) in the stack, making the stack suitable for cryogenic applications.

The present disclosure provides a chip part. The chip part includes: a capacitor portion, including a plurality of wall portions separated from each other by a plurality of trenches formed on the first main surface and having a lengthwise direction; a substrate body, formed around the capacitor portion using a portion of the semiconductor substrate; a lower electrode, disposed using at least a portion of the semiconductor substrate including the wall portions; a capacitive film, disposed along top and side surfaces of the plurality of wall portions; and an upper electrode, disposed on the capacitive film.

An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.

A package structure is provided, including a substrate, a first passivation layer, a metallization layer, a second passivation layer, and a polymer layer. The first passivation layer is formed over the substrate. The metallization layer is conformally formed on the first passivation layer. The second passivation layer is conformally formed on the first passivation layer and the metallization layer. A step structure is formed on the top surface of the second passivation layer, and includes at least one lower part that is lower than the other parts of the step structure. The polymer layer is formed over the second passivation layer. A portion of the polymer layer extends into the lower part of the step structure to engage with the step structure.

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.