The disclosed technique may be used to electrically and physically connect semiconductor wafers. The wafer may utilize a thick dielectric. Indium bumps may be deposited and patterned in a dielectric film with a small diameter, tall height and substantially uniform in size and shape. The indium can be melted to create small grain size and uniform height bumps. The dielectric film may feature trenches around the indium bumps to prevent shorting of pixels when pressed together.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure also includes a first chip structure and a second chip structure over the substrate. The chip package structure further includes an anti-warpage bar over a first portion of the first chip structure and over a second portion of the second chip structure. A width of the anti-warpage bar overlapping the second portion of the second chip structure is greater than a width of the anti-warpage bar overlapping the first portion of the first chip structure.

Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. Moreover, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.

A light emitting diode (LED) includes a n-doped semiconductor material layer, a p-doped semiconductor material layer, an active region disposed between the n-doped semiconductor layer and the p-doped semiconductor layer, and a photonic crystal grating configured to increase the light extraction efficiency of the LED.

Wafer processing techniques, or methods for forming semiconductor rides, are disclosed for fabricating plated pillar dies having die-level electromagnetic interference (EMI) shield layers. In embodiments, the method includes depositing a metallic seed layer over a semiconductor wafer and contacting die pads thereon. An electroplating process is then performed to compile plated pillars on the metallic seed layer and across the semiconductor wafer. Following electroplating, selected regions of the metallic seed layer are removed to produce electrical isolation gaps around a first pillar type, while leaving intact portions of the metallic seed layer to yield a wafer-level EMI shield layer. The semiconductor wafer is separated into singulated plated pillar dies, each including a die-level EMI shield layer and plated pillars of the first pillar type electrically isolated from the EMI shield layer.

Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar. The die interconnect may also include a low wetting layer formed on the wetting barrier.

Techniques regarding forming flip chip interconnects are provided. For example, one or more embodiments described herein can comprise a three-dimensionally printed flip chip interconnect that includes an electrically conductive ink material that is compatible with a three-dimensional printing technology. The three-dimensionally printed flip chip interconnect can be located on a metal surface of a semiconductor chip.

The present disclosure provides a method of manufacturing a semiconductor device and a semiconductor device. The method of manufacturing a semiconductor device includes: providing a substrate with trenches, and the trenches extending along a thickness direction of the substrate from a first surface of the substrate; forming a first auxiliary layer and a first conductive layer successively in the trenches, and the first conductive layer covering the first auxiliary layer; thinning the substrate on a second surface of the substrate to expose the first auxiliary layer; removing the first auxiliary layer to form first openings; forming a second medium layer on the second surface of the substrate; patterning the second medium layer to form second openings in the second medium layer, and the second openings exposing the first openings; and depositing a second initial conductive layer, the second initial conductive layer filling the first openings and the second openings.

A semiconductor package includes a semiconductor chip and a package substrate. The semiconductor chip is mounted on the package substrate. The package substrate includes a dielectric layer through which a vent hole penetrates, trace patterns disposed on the dielectric layer, and a protecting block disposed between the trace patterns and the vent hole.

A method for forming a micro bump includes the following operations. A chip at least including a silicon substrate and a Through Silicon Via (TSV) penetrating through the silicon substrate is provided. A conductive layer having a first preset size in a first direction is formed in the TSV, the first direction being a thickness direction of the silicon substrate. A connecting layer having a second preset size in the first direction is formed on a surface of the conductive layer in the TSV, where a sum of the first preset size and the second preset size is equal to an initial size of the TSV in the first direction. The silicon substrate is processed to expose the connecting layer, for forming a micro bump corresponding to the TSV.