Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.

An electronic package and a method for fabrication the same are provided. The method includes: disposing an electronic component on a substrate; forming an encapsulant layer on the substrate to encapsulate the electronic component; and forming a shielding layer made of metal on the encapsulant layer. The shielding layer has an extending portion extending to a lateral side of the substrate along a corner of the encapsulant layer, without extending to a lower side of the substrate. Therefore, the present disclosure prevents the shielding layer from coming into contact with conductive pads disposed on the lower side of the substrate and thereby avoids a short circuit from occurrence.

In one example, a semiconductor device can comprise a unit substrate comprising a unit conductive structure and a unit dielectric structure, and an electronic component coupled to the unit conductive structure. The unit substrate can comprise a portion of a singulated subpanel substrate of a panel substrate. Other examples and related methods are also disclosed herein.

The present disclosure provides a semiconductor package including a semiconductor chip and a package substrate. The semiconductor chip includes a substrate, a plurality of conductive pads in the substrate, and a plurality of conductive bumps. Each of the conductive bumps is over corresponding conductive pad. At least one of the conductive bumps proximity to an edge of the semiconductor chip is in contact with at least two discrete regions of the corresponding conductive pad. The package substrate has a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps.

A semiconductor package includes: a second semiconductor chip including a second through electrode that penetrates a second body portion and a second connection electrode that is connected to one end of the second through electrode; a first semiconductor chip stack disposed over the second semiconductor chip and including a plurality of first semiconductor chips, each of the plurality of first semiconductor chips includes a first through electrode and a first connection electrode connected to one end of the first through electrode; a molding layer; a third semiconductor chip disposed over the molding layer and the first semiconductor chip stack; and an external connection electrode electrically connected to an other end of the second through electrode, wherein, the second semiconductor chip and the plurality of first semiconductor chips are electrically connected through the second through electrode, the second connection electrode, the first through electrodes, and the first connection electrodes.

A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

Disclosed is a method for manufacturing an electronic component device, including: preparing a sealing structure having a sealing layer having two opposing main surfaces, an electronic component, and a connection portion, the connection portion being exposed on a circuit surface that is one main surface of the sealing layer; preparing a rewiring structure having a rewiring portion having two opposing main surfaces, and a plurality of bumps; and bonding the sealing structure and the rewiring structure in a direction that the circuit surface and the plurality of bumps face each other, with an insulating layer intervening.

A gold powder comprising gold having a purity of 99.9% by mass or more and having an average particle size of 0.01 μm or more and 1.0 μm or less, a content of a chloride ion is 100 ppm or less, and a content of a cyanide ion is 10 ppm or more and 1000 ppm or less. A total of the content of a chloride ion and the content of a cyanide ion is preferably 110 ppm or more and 1000 ppm or less. The gold powder has improved adaptability to various processes including bonding or the like with a content of a chloride ion, that is, an impurity, optimized. A gold paste using this gold powder is suitably used in various uses for bonding such as die bonding of a semiconductor chip, sealing a semiconductor package, and forming an electrode/wire.

A chip package structure includes a glass substrate, a routing layer, and a plurality of dies. A first surface of the glass substrate has solder joints and a second surface of the glass substrate has substrate solder balls. The routing layer is located in the glass substrate, and the solder joints are electrically connected to the substrate solder balls by using the routing layer. Each die has chip solder balls, is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls. The embodiments can improve connection reliability between the die and the glass substrate and can reduce a signal transmission loss.