An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.

An integrated circuit component including a semiconductor die, a plurality of conductive vias and a protection layer is provided. The semiconductor die includes an active surface and a plurality of conductive pads disposed on the active surface. The conductive vias are respectively disposed on and in contact with the conductive pads, wherein each conductive via of a first group of the conductive vias has a first maximum size, each conductive via of a second group of the conductive vias has a second maximum size, and the first maximum size is less than the second maximum size in a vertical projection on the active surface. The protection layer covers the active surface and is at least in contact with sidewalls of the conductive vias.

A semiconductor device comprising a wiring member with which a semiconductor chip is electrically connected including: a first wiring layer having a plurality of first conductive patterns; a second wiring layer arranged next to the first wiring layer in a thickness direction of the wiring member, and having a second conductive pattern; and a third wiring layer arranged next to the second wiring layer in the thickness direction of the wiring member, and having a third conductive pattern. Here, in plan view, a first opening portion of each of two, which are arranged next to each other, of a plurality of first opening portions each penetrating through the second conductive pattern is overlapped with a pair of differential signal wirings contained in plurality of first conductive patterns, and is overlapped with two or more of a plurality of second opening portions each penetrating through the third conductive pattern.

A semiconductor device includes a wiring substrate provided with a plurality of pads electrically connected to a semiconductor chip in a flip-chip interconnection. The wiring substrate includes a pad forming layer in which a signal pad configured to receive transmission of a first signal and a second pad configured to receive transmission of a second signal different from the first signal are formed and a first wiring layer located at a position closest to the pad forming layer. In the wiring layer, a via land overlapping with the signal pad, a wiring connected to the via land, and a wiring connected to the second pad and extending in an X direction are formed. In a Y direction intersecting the X direction, a width of the via land is larger than a width of the wiring. A wiring is adjacent to the via land and overlaps with the signal pad.

Devices and methods that can facilitate hybrid under-bump metallization components are provided. According to an embodiment, a device can comprise an under-bump metallization component that can comprise a superconducting interconnect component and a solder wetting component. The device can further comprise a solder bump that can be coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component can comprise a hermetically sealed superconducting interconnect component.

Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to a qualified stacked silicon interconnect (SSI) technology programmable integrated circuit (IC) region by providing an interface (e.g., an HBM buffer region implemented with a hierarchical switch network) between the added feature device and the programmable IC region. One example apparatus generally includes a programmable IC region and an interface region configured to couple the programmable IC region to at least one fixed feature die via a first plurality of ports associated with the at least one fixed feature die and a second plurality of ports associated with the programmable IC region. The interface region is configured as a switch network between the first plurality of ports and the second plurality of ports, and the switch network includes a plurality of full crossbar switch networks.

Devices and methods that can facilitate hybrid under-bump metallization components are provided. According to an embodiment, a device can comprise an under-bump metallization component that can comprise a superconducting interconnect component and a solder wetting component. The device can further comprise a solder bump that can be coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component can comprise a hermetically sealed superconducting interconnect component.

A film-type semiconductor package includes a metal lead portion arranged on a film substrate, a semiconductor chip including a pad, and a bump connecting the metal lead portion to the pad of the semiconductor chip. The bump includes a metal pillar arranged on the pad and including a first metal and a soldering portion arranged on an entire surface of the metal pillar, bonded to the metal lead portion, and including the first metal and a second metal that is different from the first metal.

An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.

An electronic device is provided. The electronic device includes: a substrate, a first light-emitting element, and a second light-emitting element. The first light-emitting element is disposed on the substrate and configured to emit a first color light under a first current density when the substrate provides a first current to the first light-emitting element. The second light-emitting element is disposed on the substrate and configured to emit a second color light under a second current density when the substrate provides a second current to the second light-emitting element. The first current is equal to the second current, and the first current density is different from the second current density.