A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

An electronic device is provided. The electronic device includes a substrate and another substrate disposed opposite to the substrate. The electronic device includes a first light-emitting element disposed on the substrate and configured to emit blue light under a first current density when the substrate provides a first current to the first light-emitting element. The electronic device includes a second light-emitting element disposed on the substrate and configured to emit green light or red light under a second current density when the substrate provides a second current to the second light-emitting element. The electronic device includes a protective layer disposed between the substrate and the another substrate and covering the first light-emitting element and the second light-emitting element. The electronic device includes an adhesive layer disposed between the protective layer and the another substrate.

A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.

A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace having a trace width measured in a direction perpendicular to a lengthwise direction of the first metal trace. The first package component further includes a second metal trace at the surface of the first package component. The first metal trace and the second metal trace are parallel to each other. A second package component is overlying the first package component, wherein the second package component includes a metal bump. A solder region bonds the metal bump to the first metal trace, wherein the solder region contacts a top surface and sidewalls of the first portion of the first metal trace. A ratio of a volume of the solder region to the trace width is between about 1,100 m.sup.2 and about 1,300 m.sup.2.

The invention discloses a voltage controlled oscillator (VCO) based on hybrid resonator, including a hybrid resonator and a negative resistance circuit, wherein the hybrid resonator includes the first LC series resonance branch, the second LC series resonance branch and the third LC series resonance branch. The first LC series resonance branch and the second LC series resonance branch forms a parallel structure, in which one end of the said parallel structure is grounded while the other end is connected to the third LC series resonance branch, and the other end of the third LC series resonance branch is connected to the negative resistance circuit. The resonance frequency of the first LC series resonance branch is lower than that of the second LC series resonance branch. The invented VCO can effectively improve the phase noise, especially maintain a good phase noise with the increase of the tuning frequency.

An integrated circuit component including a semiconductor die, a plurality of conductive vias and a protection layer is provided. The semiconductor die includes an active surface and a plurality of conductive pads disposed on the active surface. The conductive vias are respectively disposed on and in contact with the conductive pads, wherein each conductive via of a first group of the conductive vias has a first maximum size, each conductive via of a second group of the conductive vias has a second maximum size, and the first maximum size is less than the second maximum size in a vertical projection on the active surface. The protection layer covers the active surface and is at least in contact with sidewalls of the conductive vias.

An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.

A film-type semiconductor package includes a metal lead portion arranged on a film substrate, a semiconductor chip including a pad, and a bump connecting the metal lead portion to the pad of the semiconductor chip. The bump includes a metal pillar arranged on the pad and including a first metal and a soldering portion arranged on an entire surface of the metal pillar, bonded to the metal lead portion, and including the first metal and a second metal that is different from the first metal.

Aspects of this disclosure relate to a first die includes an LC resonant circuit including a first capacitive element, such as a capacitor or a varactor, and an inductive element. The LC resonant circuit is configured to generate a signal having a frequency of oscillation. The first die includes bump pads electrically coupled to both ends of the first capacitive element. A second die can be flip chip mounted on the first die. Bumps can electrically connect a second capacitive element of the second die in parallel with the first capacitive element of the first die. This can increase the Q factor of the LC resonant circuit.