Provided is a bonding joining structure in which a heat generating body and a support including a metal are joined to each other via a joint portion composed of a sintered body of copper powder. The support contains copper or gold, the copper or gold being present in at least an outermost surface of the support. An interdiffusion portion in which copper or gold contained in the support and copper contained in the sintered body is formed so as to straddle a bonding interface between the support and the sintered body. Preferably, a copper crystal structure having the same crystal orientation is formed in the interdiffusion portion so as to straddle the bonding interface.

A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.

A gold powder comprising gold having a purity of 99.9% by mass or more and having an average particle size of 0.01 ?m or more and 1.0 ?m or less, a content of a chloride ion is 100 ppm or less, and a content of a cyanide ion is 10 ppm or more and 1000 ppm or less. A total of the content of a chloride ion and the content of a cyanide ion is preferably 110 ppm or more and 1000 ppm or less. The gold powder has improved adaptability to various processes including bonding or the like with a content of a chloride ion, that is, an impurity, optimized. A gold paste using this gold powder is suitably used in various uses for bonding such as die bonding of a semiconductor chip, sealing a semiconductor package, and forming an electrode/wire.

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

A semiconductor structure and a method of forming include a first semiconductor die and a first dummy die over a carrier, wherein a thickness of the first semiconductor die is greater than a thickness of the first dummy die, a first molding compound layer over the carrier, the first molding compound layer extending along sidewalls of the first semiconductor die and the first dummy die and a first interconnect structure over the first molding compound layer, wherein the first interconnect structure comprises a first metal feature electrically coupled to the first semiconductor die and the first molding compound layer is formed between the first dummy die and the first metal feature.

A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

Methods/structures of joining package structures are described. Those methods/structures may include forming a metal formate on a surface of a first solder interconnect structure disposed on a first package substrate at a first temperature, and attaching a second solder interconnect structure disposed on a second package substrate to the first solder interconnect structure at a second temperature. The second temperature decomposes at least a portion of the metal formate and generates a hydrogen gas. The generated hydrogen gas removes an oxide from the second solder interconnect structure during joint formation at the second temperature.

A resin composition is provided, including a binder resin, and silver-coated particles in which a functional group is introduced to a surface. A ratio (a/b) of Young's modulus (a) of the silver-coated particles to Young's modulus (b) of the binder resin after being cured is 0.1 to 2.0, and the Young's modulus (a) of the silver-coated particles is 0.05 to 2.0 GPa.

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a system comprises a semiconductor component including an interposer substrate, a microelectronic die over the interposer substrate, and a connection structure composed of a volume of solder material between the interposer substrate and the microelectronic die. The connection structure can include at least one of (a) a single, unitary structure covering approximately all of the back side of the microelectronic die, and (b) a structure electrically isolated from internal active features of the microelectronic die. In some embodiments, the connection structure can be positioned to provide generally consistent stress distribution within the system.