A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view.

The present invention has an object to achieve bonding which satisfies both in heat resistivity and in stress-relaxation ability, and the bonding material according to this invention is a sheet-like bonding material 1 made of a silver-bismuth alloy which, when heated in a state being in contact with a metal material as a bonding target (for example, surface layers 2f, 3f), forms in the metal material (as its material, for example, gold, silver or copper) a diffusion layer Ld2, Ld3 of silver due to solid-phase diffusion reaction, so as to be bonded to the metal material, said bonding material being characterized by containing not less than 1 mass % but not more than 5 mass % of bismuth.

A power semiconductor device includes a plurality of power semiconductor elements constituting upper and lower arms of an inverter circuit, a first sealing member sealing the plurality of power semiconductor elements, a positive electrode-side terminal and a negative electrode-side terminal each connected with any of the plurality of power semiconductor elements and protruding from the first sealing member, a second sealing member sealing at least a part of the positive electrode-side terminal and at least a part of the negative electrode-side terminal, and a case in which the power semiconductor elements sealed with the first sealing member are housed.

A ground strap for grounding electrical cables for protection against at least one of EMI, RFI or ESD and method of construction thereof is provided. The ground strap has a wall with opposite edges extending along a lengthwise direction between opposite ends. The wall is formed from a plurality of interlaced filaments, with at least some of the plurality of interlaced filaments including a plurality of electrically conductive filaments interlaced in electrical communication with one another.

A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.

A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view.

In one embodiment, a stack die package can include a lead frame and a first die including a gate and a source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. The gate and source are flip chip coupled to the lead frame. The stack die package can include a second die including a gate and a drain that are located on a first surface of the second die and a source that is located on a second surface of the second die that is opposite the first surface. The source of the second die is facing the drain of the first die.

In various embodiments, a package may be provided. The package may include a chip carrier. The package may further include a chip arranged over the chip carrier. The package may also include encapsulation material encapsulating the chip and partially the chip carrier. A coolant receiving recess may be provided over the chip in the encapsulation material, wherein the coolant receiving recess is configured to receive coolant.

The power module includes: a first metallic circuit pattern, a semiconductor device disposed on the first metallic circuit pattern; a leadframe electrically connected to the semiconductor device; and a stress buffering layer disposed on an upper surface of the semiconductor device, and capable of buffering a CTE difference between the semiconductor device and the leadframe. The leadframe is connected to the semiconductor device via the stress buffering layer, a CTE of the stress buffering layer is equal to or less than a CTE of the leadframe, and a cross-sectional shape of the stress buffering layer is L-shape. There is provided: the power module capable of realizing miniaturization and large current capacity, and reducing cost thereof by using leadframe structure, and capable of reducing a variation in welding and improving a yield without damaging a semiconductor device; and a fabrication method for such a power module.

A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.