A semiconductor package may include: a chip stack including first to N.sup.th semiconductor chips having first to N.sup.th chip pads formed in active surfaces thereof, respectively, and sequentially stacked in a vertical direction such that the first to N.sup.th chip pads are exposed, wherein N is a natural number equal to or more than 2; first to N.sup.th vertical wires having first ends connected to the first to N.sup.th chip pads, respectively, and extended in the vertical direction; a coating layer surrounding portions of the first to k.sup.th vertical wires, extended from the first ends, among the first to N.sup.th vertical wires, and connection portions between the first ends of the first to k.sup.th vertical wires and the first to k.sup.th chip pads; and a molding layer covering the chip stack, surrounding the vertical wires, and covering the coating layer.

A versatile, thermally stable and economically effective corrosion inhibition treatment for copper (Cu) metal and selected metals surface through a single step chemical vapor deposition (CVD) of selected inhibitor compounds at temperatures as low as 100-200 C. is described in this invention. The resulting CVD deposited inhibition coating is thermally stable to 300 C. and protects Cu and selected metals from active corrosion in various technologically important operational environments. The selective coating for copper metal is achieved by controlling the chemistry of bonding between the Copper metal surface and inhibitor material used. The technique can be accomplished by using one or more inhibitors separately or in combination in order to create an all-terrain stable & robust corrosion prevention coating for copper metal.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

A semiconductor device includes a semiconductor element having a surface electrode layer; a first wire that is electrically connected to the first main surface of the surface electrode layer at a plurality of first connecting portions and is arranged in a first direction on the first main surface; and a second wire that is electrically connected to the first main surface of the surface electrode layer at a second connecting portion and is arranged in a second direction on the first main surface, wherein a second circle equivalent diameter, which is a diameter of a circle having a same cross-sectional area as the second wire, is larger than a first circle equivalent diameter, which is a diameter of a circle having a same cross-sectional area as the first wire.

A method for fabricating a radio-frequency (RF) module is disclosed, the method including forming or providing a first assembly that includes a packaging substrate and an RF component mounted thereon, the first assembly further including one or more shielding-wirebonds formed relative to the RF component, forming an overmold over the packaging substrate to substantially encapsulate the RF component and the one or more shielding-wirebonds, the overmold formed by compression molding, and forming a conductive layer on an upper surface of the overmold such that the conductive layer is in electrical contact with some or all of the shielding-wirebonds.

A method for processing an ultra-high density interconnect wire under light source guidance, comprising preparing a photo-thermal response conductive paste, and putting it into an air pressure injector; driving the air pressure injector; the air pressure injector extrudes the photo-thermal response conductive paste, so that the photo-thermal response conductive paste is connected with the first chip to form an interconnection wire; stopping extruding the photo-thermal response conductive paste, and driving the air pressure injector to pull off the interconnection wire; a linear light source emits light and irradiates on the interconnection wire to bend to an upper side of a second chip bonding pad; an extrusion mechanism presses a free end of the interconnection wire on the second chip bonding pad; the first chip and the second chip are subjected to glue dripping encapsulation.

A package and method of making a package is disclosed. In one example, the package includes an electronic chip having at least one pad, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive contact element extending from the at least one pad and through the encapsulant so as to be exposed with respect to the encapsulant. The electrically conductive contact element comprises a first contact structure made of a first electrically conductive material on the at least one pad and comprises a second contact structure made of a second electrically conductive material and being exposed with respect to the encapsulant. At least one of the at least one pad has at least a surface portion which comprises or is made of the first electrically conductive material.

A method for manufacturing a bonding wire includes: putting a surface layer metal of a bonding wire in a crucible having a die cooler provided at the lower part thereof and melting the same; putting a main component metal core of the bonding wire in a core guide located at the upper part of the die cooler of the crucible and heating the core guide to the melting point or below of the metal core; transferring the metal core toward the die cooler so as to allow the molten surface layer metal to be injected to the surface of the metal core; and manufacturing a 50 m to 350 m bonding wire from the cast wire precursor by using a drawing die.

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

A semiconductor device includes a first metal film forming an uppermost layer wiring that has a bonding pad. A concentration of impurities at a crystal grain boundary of the first metal film is higher than a concentration of impurities in crystal grains in the first metal film. The maximum grain size of crystal grains included in the first metal film is less than 5 m.