A wiring structure includes an upper conductive structure, a lower conductive structure and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The at least one lower dielectric layer of the lower conductive structure is substantially free of glass fiber. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.

A semiconductor device includes an insulation substrate including a circuit pattern, semiconductor chips mounted on the circuit pattern, a wire connecting between the semiconductor chips and between the semiconductor chip and the circuit pattern, and a conductive material serving as a conductor formed integrally with the wire.

The present invention provides a Cu alloy bonding wire for a semiconductor device, where the bonding wire can satisfy requirements of high-density LSI applications. In the Cu alloy bonding wire for a semiconductor device, the abundance ratio of a crystal orientation <110> having an angular difference of 15 degrees or less from a direction perpendicular to one plane including a wire center axis to crystal orientations on a wire surface is 25% or more and 70% or less in average area percentage.

A semiconductor module is provided, including: a semiconductor chip having an upper surface electrode and a lower surface electrode opposite to the upper surface electrode; a metal wiring plate electrically connected to the upper surface electrode of the semiconductor chip; and a sheet-like low elastic sheet provided on the metal wiring plate, the low elastic sheet having elastic modulus lower than that of the metal wiring plate. A manufacturing method for a semiconductor module is provided, including: providing a semiconductor chip; solder-bonding a metal wiring plate above said semiconductor chip; and applying a sheet-like low elastic sheet having the elastic modulus lower than that of said metal wiring plate to said metal wiring plate.

A process to fabricate ultra-fine grain metal wire, comprising: inserting a plurality of metal strands into a flexible elastic polyurethane sheath having an accommodating slot for each of the strands of metal to form a sheathed strand assembly; equal channel angular pressing (ECAP pressing) the sheathed strand assembly through an ECAP die having a plurality of die channels corresponding to the plurality of metal strands. The process is designed to improve electric conductance and mechanical properties of elongated metal parts and is especially applicable to optimize the conductance and tensile strength of copper cables, wires, strings, and rods.

A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.

A wire bonding method, comprising the steps of: extending a length of bonding wire from a capillary to form a wire tail; deforming a point on the wire tail to form a weakened portion between the wire tail and a remainder of the bonding wire retained within the capillary; and retracting at least a portion of the wire tail including the weakened portion into the capillary prior to bonding the wire tail to at least one of a bonding pad and a substrate.

An apparatus and method for reducing the volume of a resource allocation information message in a broadband wireless communication system are provided. The method includes transmitting a message including information indicating a periodicity of an uplink control channel for an initial network entry; and receiving an uplink signal for the initial network entry through the uplink control channel.

An apparatus and method for reducing the volume of a resource allocation information message in a broadband wireless communication system are provided. The method includes transmitting a message including information indicating a periodicity of an uplink control channel for an initial network entry; and receiving an uplink signal for the initial network entry through the uplink control channel.

An electronic device of the present disclosure includes: a first resin layer (21) having a first resin layer main surface and a first resin layer inner surface; a columnar conductor having a columnar conductor main surface and a columnar conductor inner surface and penetrating the first resin layer in direction z; a wiring layer connecting the first resin layer main surface and the first conductor main surface; an electronic component having a component main surface facing the same side as the first resin layer main surface and a component inner surface facing the same side as the first resin layer inner surface and being electrically connected and joined to the wiring layer; a second resin layer having a second resin layer main surface facing the same direction as the first resin layer main surface and a second resin layer inner surface being in contact with the first resin layer main surface, covering the wiring layer and the electronic component; and an external electrode closer to the side where the first resin layer inner surface faces than the first resin layer and is electrically connected to the columnar conductor.