An electronic device includes a first substrate, a second substrate, a first conductive element, a second conductive element and a third conductive element. The first substrate has a top surface and a first side surface. The second substrate is oppositely disposed on the first substrate and has a second side surface parallel to the first side surface. The first conductive element and the third conductive element are disposed on the top surface of the first substrate. The second conductive element is disposed on the first side surface of the first substrate and the second side surface of the second substrate. The third conductive element contacts the first conductive element to define a first contact area, the third conductive element contacts the second conductive element to define a second contact area, and the first contact area is greater than the second contact area.

An electronic package is provided, in which an electronic component with a conductive layer on an outer surface thereof is embedded in an encapsulant, where at least one electrode pad is disposed on an active surface of the electronic component, and at least one wire electrically connected to the electrode pad is arranged inside the electronic component, so that the conductive layer is electrically connected to the wire, such that the electrode pad, the wire and the conductive layer are used as a power transmission structure which serves as a current path to reduce DC resistance and improve an impedance issue associated with the supply of power.

An object of the present invention is to provide an Ag alloy bonding wire for a semiconductor device capable of extending the high-temperature life of a wire, reducing chip damage during ball bonding, and improving characteristics such as ball bonding strength in applications of on-vehicle memory devices. The Ag alloy bonding wire for a semiconductor device according to the present invention contains one or more of In and Ga for a total of 110 at ppm or more and less than 500 at ppm, and one or more of Pd and Pt for a total of 150 at ppm or more and less than 12,000 at ppm, and a balance being made up of Ag and unavoidable impurities.

The present disclosure provides a chip package structure having a heat sink and a method making the same. The method includes: bonding a chip to a top surface of a package substrate and forming a heat-conducting lead having an arc-shape and placed on the chip in a vertical direction, a first end of the heat-conducting lead is connected with a surface of the chip, and a second end is connected with a solder ball; forming a plastic package material layer that protects the chip and the heat-conducting lead; forming a heat-conducting adhesive layer on the surface of the plastic package material layer, where the heat-conducting adhesive layer is connected with the solder ball on the second end of the heat-conducting lead; and forming a heat dissipation layer on a surface of the heat-conducting adhesive layer. With the present disclosure, the heat dissipation efficiency of the chip is effectively improved.

A semiconductor package includes a conductive pad, a semiconductor die with an aluminum bond pad over a dielectric layer of the semiconductor die, a gold bump on the aluminum bond pad, a first intermetallic layer of gold and aluminum between the aluminum bond pad and the gold bump, a copper ball bond on the gold bump, a second intermetallic layer of copper and gold between the copper ball bond and the gold bump, a copper wire extending from the copper ball bond to the conductive pad, a stitch bond between the copper wire and the conductive pad.

A semiconductor module includes a substrate, a semiconductor die arranged on the substrate, at least one first bond wire loop, wherein both ends of the at least one first bond wire loop are arranged on and coupled to a first electrode of the semiconductor die, and a molded body encapsulating the semiconductor die, wherein a top portion of the at least one first bond wire loop is exposed from a first side of the molded body.

There is provided an Al wiring material which suppresses a chip crack and achieves thermal shock resistance while suppressing lowering of a yield at the time of manufacture. The Al wiring material contains at least Sc and Zr so as to satisfy 0.01≤x1≤0.5 and 0.01≤x2≤0.3 where x1 is a content of Sc [% by weight] and x2 is a content of Zr [% by weight], with the balance comprising Al.

A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

A bonding wire includes a hollow member made of an insulator and mounted such as to bridge ICs formed with interconnects, such that a plurality of open ends is each closed by abutting on a surface of the interconnect that is a connection target, and a connection member made of a conductor, filling inside of the hollow member such as to bond to the surface of the interconnect at a location where the hollow member abuts on the surface of the interconnect.

A display substrate, including: a base substrate including at least a side edge and a display area; a plurality of pixel units disposed in the display area, a second pixel unit is located on a side of a first pixel unit close to the side edge, edges of the second pixel unit include the side edge, a third pixel unit is located between the first pixel unit and the second pixel unit, and the third pixel unit is adjacent to the second pixel unit; and a plurality of light emitting diode chips disposed on the base substrate a first light emitting diode chip is located in the first pixel unit, a part of a second light emitting diode chip is located in the second pixel unit, and the other part of the second light emitting diode chip is located in the third pixel unit.