Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a package substrate, a redistribution layer on the package substrate, a vertical connection terminals that connects the package substrate to the redistribution layer, a first semiconductor chip between the package substrate and the redistribution layer, a first molding layer that fills a space between the package substrate and the redistribution layer, a second semiconductor chip on the redistribution layer, a third semiconductor chip on the second semiconductor chip, a first connection wire that directly and vertically connects the redistribution layer to a first chip pad of the third semiconductor chip, the first chip pad is beside the second semiconductor chip and on a bottom surface of the third semiconductor chip, and a second molding layer on the redistribution layer and covering the second semiconductor chip and the third semiconductor chip.

An interposer, which is used to connect two circuit boards, includes an inner structure (10), an outer structure (20), and a protective layer (50). The inner structure (10) includes a first base layer (11) and a first wiring layer (131) formed on the first base layer (11). The outer structure (20) includes a second base layer (21) and a second wiring layer (231) formed on the second base layer (21). An end portion of at least wiring line of the first wiring layer (131) and the second wiring layer (231) extends to a sidewall of the interposer (100). An end of another wiring line extends to the other sidewall of the interposer (100). The first wiring layer (131) is electrically connected to the second wiring layer (231) by a conductive blind hole (41).

There is provided a copper bonding wire that exhibits a favorable bondability even when a scrub at the time of bonding is reduced. The copper bonding wire is characterized in that when a sum of percentages of Cu, Cu.sub.2O, CuO and Cu(OH).sub.2 on a surface of the wire as measured by X-ray Photoelectron Spectroscopy (XPS) is defined as 100%, Cu[II]/Cu[I] which is a ratio of a total percentage of CuO and Cu(OH).sub.2 (Cu[II]) corresponding to bivalent Cu to a percentage of Cu.sub.2O (Cu[I]) corresponding to monovalent Cu falls within a range from 0.8 to 12.

There is provided an Ag alloy bonding wire for semiconductor devices which exhibits a favorable bond reliability in a high-temperature environment even when using a mold resin of high S content and can suppress a chip damage at the time of ball bonding. The Ag alloy bonding wire is characterized by containing at least one element selected from the group consisting of Pd and Pt (hereinafter referred to as a “first element”) and at least one element selected from the group consisting of P, Cr, Zr and Mo (hereinafter referred to as a “second element”) so as to satisfy

[00001]$0.05\le \text{x}1\le 3.0,\text{and}$

[00002]$15\le \text{x}2\le 700$

where x1 is a total concentration of the first element [at.%] and x2 is a total concentration of the second element [at. ppm], with the balance including Ag.

There is provided an Al bonding wire which can achieve a sufficient bonding reliability of bonded parts of the bonding wire under a high temperature state where a semiconductor device using the Al bonding wire is operated. The Al bonding wire contains 0.01 to 1% of Sc, and further contains 0.01 to 0.1% in total of at least one or more of Y, La, Ce, Pr and Nd. With regard to the Al bonding wire, a recrystallization temperature thereof is increased, so that the proceeding of recrystallization of the bonding wire can be suppressed, and strength of the wire can be prevented from being decreased even when the semiconductor device is continuously used under a high temperature environment. Accordingly, the Al bonding wire can sufficiently secure the reliability of the bonded parts after a high-temperature long-term hysteresis.

The present disclosure is directed to a semiconductor die with multiple contact pads electrically coupled to a single lead via a single wire, and methods for fabricating the same. In one or more embodiments, multiple contact pads are electrically coupled to each other by a plurality of conductive layers stacked on top of each other. The uppermost conductive layer is then electrically coupled to a single lead via a single wire.

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.

A semiconductor package includes a semiconductor die having an active surface and a bottom surface opposite to the active surface; a plurality of bond pads distributed on the active surface of the semiconductor die; an encapsulant covering the active surface of the semiconductor die, wherein the encapsulant comprises a bottom surface that is flush with the bottom surface of the semiconductor; and a plurality of printed interconnect features embedded in the encapsulant for electrically connecting the plurality of bond pads. Each of the printed interconnect features comprises a conductive wire and a conductive pad being integral with the conductive wire.

A method of manufacturing an electronic device is provided, wherein the method includes the following steps. A first substrate is provided, wherein the first substrate has a top surface and a side surface. A first wire is formed on the top surface of the first substrate. An auxiliary bonding pad is formed on the top surface of the first substrate, and the auxiliary bonding pad contacts the first wire. A second wire is formed on the side surface of the first substrate, and the second wire contacts the auxiliary bonding pad. The second wire and the auxiliary bonding pad include at least one same material.

Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.