A fan-out semiconductor package module includes: a structure including a wiring member including wiring patterns, one or more first passive components disposed on the wiring member and electrically connected to the wiring pattern, and a first encapsulant encapsulating at least portions of each of the one or more first passive components, and having a first through-hole penetrating through the wiring member and the first encapsulant; a semiconductor chip disposed in the first through-hole of the structure and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; a second encapsulant encapsulating at least portions of the semiconductor chip and filling at least portions of the first through-hole; and a connection member disposed on the structure and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads and the wiring patterns.

A light emitting apparatus according to an embodiment of the present technology includes a base portion, a light emitting element, and a cover portion. The base portion includes a support surface. The light emitting element is disposed on the support surface of the base portion. The cover portion includes a light transmission portion through which light emitted from the light emitting element is transmitted and a protrusion portion which is provided on at least a part of a periphery of the light transmission portion and protruded relative to the light transmission portion, the cover portion being provided on the support surface in such a manner as to cover the light emitting element.

A wire comprising a wire core with a surface, the wire core having a coating layer superimposed on its surface, wherein the wire core includes: (a) pure silver consisting of silver and further components; or (b) doped silver consisting of silver, at least one doping element, and further components; or (c) a silver alloy consisting of silver, palladium and further components; or (d) a silver alloy consisting of silver, palladium, gold, and further components; or (e) a doped silver alloy consisting of silver, palladium, gold, at least one doping element, and further components, wherein the individual amount of any further component is less than 30 wt.-ppm and the individual amount of any doping element is at least 30 wt.-ppm, and the coating layer is a single-layer of gold or palladium or a double-layer comprised of an inner layer of nickel or palladium and an adjacent outer layer of gold.

A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.

The present disclosure provides a three-dimensional stacked fan-out packaging structure and a method making the same. The structure includes: a first semiconductor chip, a first packaging material layer, a metal connecting pillar, a first rewiring layer, a second rewiring layer, a second semiconductor chip, solder ball bumps, an underfill layer under the second semiconductor chip, and a second packaging material layer. The formed three-dimensional stacked fan-out packaging structure can package two sets of fan-out wafers in the three-dimensional direction. A single package stacked up after die-cutting has two sets of chips in the third-direction. The electrical signals of all chips in a single package can be controlled by arranging a first rewiring layer, a metal connecting post, and the second rewiring layer, so that more chips can be packaged in a single package, the integration of the package is improved, and the package volume can shrink.

A method includes providing a first lead frame that includes a first die pad and a first row of leads, providing a connection lug, mounting a first semiconductor die on the first die pad, the first semiconductor die including first and second voltage blocking terminals, electrically connecting the connection lug to one of the first and second voltage blocking terminals, electrically connecting a first one of the leads from the first row to an opposite one of the first and second voltage blocking terminals, and forming an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die. After forming the encapsulant body, the first row of leads each protrude out of a first outer face of the encapsulant body and the connection lug protrudes out of a second outer face of the encapsulant body.

A semiconductor package structure includes a substrate, and a package preform. The substrate includes a plurality of conductive tracing wires. The package preform includes a semiconductor chip and a plurality of binding wires. The semiconductor chip includes a plurality of welding spots, and the welding spots are electrically connected with corresponding conductive tracing wires by the binding wires. Each binding wire comprises a carbon nanotube composite wire, the carbon nanotube composite wire includes a carbon nanotube wire and a metal layer. The carbon nanotube wire consists of a plurality of carbon nanotubes spirally arranged along an axial direction an axial direction of the carbon nanotube wire.

An electro-optical package. In some embodiments, the package includes: a carrier; a first integrated circuit, on the carrier; a first bonding layer, between the carrier and the first integrated circuit; a thermoelectric cooler, on the carrier; a second integrated circuit, on the thermoelectric cooler; and a first wire bond. The first wire bond may connect a first pad, on the first integrated circuit, to a second pad, on the second integrated circuit, the first pad and the second pad having a height difference less than 100 microns.

A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.

A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.