An improved system for measuring current within a power semiconductor module is disclosed, where the system is integrated within the power module. The system includes a point field detector sensing a magnetic field resulting from current flowing in one phase of the module. A lead frame conductor may be provided to shape the magnetic field and minimize the influence of cross-coupled magnetic fields from currents conducted in other power semiconductor devices within one phase of the module. Optionally, a second point field detector may be provided at a second location within the module to sense a magnetic field resulting from the current flowing in the same phase of the module. Each phase of the power module includes at least one point field detector. A decoupling circuit is provided to decouple multiple currents flowing within the same phase or to decouple currents flowing within different phases of the power module.

An optoelectronic component includes a semiconductor chip, the semiconductor chip emitting infrared radiation; a reflector that reflects the infrared radiation of the semiconductor chip; and a filter configured in the form of a coating, the filter being transparent for the infrared radiation of the semiconductor chip, wherein visible light striking the optoelectronic component being absorbed to at least 75%.

A semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side. The second metal oxide semiconductor transistor includes the same structure as the first metal oxide semiconductor transistor. A conductor that connects the drains of the first and second metal oxide semiconductor transistors is provided in the other major surface of the semiconductor device.

A module assembly includes an adapter substrate with at least one cavity and a surface mounted die mounted on a top surface of the adapter substrate. The first cavity extends through the adapter substrate and has at least one first side wall. A first metallization layer is provided within the cavity. A first recessed die is attached to the first metallization layer and mounted within the cavity such that the first recessed die is at least partially recessed into the first cavity and surrounded by a gap filler that resides between side portions of the first recessed die and the at least one first side wall. The top surface of the gap filler is flush with the top surface of the adapter substrate and a top surface of the first recessed die.

A semiconductor package structure includes a substrate, and a package preform. The substrate includes a plurality of conductive tracing wires. The package preform includes a semiconductor chip and a plurality of binding wires. The semiconductor chip includes a plurality of welding spots, and the welding spots are electrically connected with corresponding conductive tracing wires by the binding wires. Each binding wire comprises a carbon nanotube composite wire, the carbon nanotube composite wire includes a carbon nanotube wire and a metal layer. The carbon nanotube wire consists of a plurality of carbon nanotubes spirally arranged along an axial direction an axial direction of the carbon nanotube wire.

Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.

Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.

A semiconductor apparatus includes elements formed on a substrate, a first insulation layer, a first pad and a second pad arranged on the first insulation layer and located above the elements, and a second insulation layer that is arranged on the side surfaces and upper surfaces of the first pad and the second pad. The second insulation layer includes openings at upper surfaces of the first pad and the second pad. The thickness of the first pad and the second pad is 2 m or more, the thickness of the second insulation layer is less than or equal to of the thickness of the first pad and the second pad, and the distance between the first pad and the second pad is greater than or equal to four times the thickness of the first pad and the second pad.

A semiconductor module includes a first power semiconductor device, a conductive wire, and a resin film. The conductive wire is joined to a surface of a first front electrode of the first power semiconductor device. The resin film is formed to be continuous on at least one of an end portion or an end portion of a first joint between the first front electrode and the conductive wire in a longitudinal direction of the conductive wire, a surface of the first front electrode, and a surface of the conductive wire. The resin film has an elastic elongation rate of 4.5% to 10.0%.

Apparatuses relating generally to a vertically integrated microelectronic package are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface. A first microelectronic device is coupled to the upper surface of the substrate. The first microelectronic device is a passive microelectronic device. First wire bond wires are coupled to and extend away from the upper surface of the substrate. Second wire bond wires are coupled to and extend away from an upper surface of the first microelectronic device. The second wire bond wires are shorter than the first wire bond wires. A second microelectronic device is coupled to upper ends of the first wire bond wires and the second wire bond wires. The second microelectronic device is located above the first microelectronic device and at least partially overlaps the first microelectronic device.