While a substrate is placed on a substrate placement stage provided in a central substrate transfer unit, the substrate is transferred to a component loading operation unit, after operation for loading a component on the substrate has been performed by the component loading operation unit, the central substrate transfer unit is moved to the side of a first component crimping operation unit to thereby transfer the substrate that remains placed on the substrate placement stage to the first component crimping operation unit, and the component is crimped to the substrate by the first component crimping operation unit.

A method is provided to fabricate a high-power module. A non-touching needle is used to paste a slurry on a heat-dissipation substrate. The slurry comprises nano-silver particles and micron silver particles. The ratio of the two silver particles is 9:1˜1:1. The slurry is pasted on the substrate to be heated up to a temperature kept holding. An integrated chip (IC) is put above the substrate to form a combined piece. A hot presser processes thermocompression to the combined piece to form a thermal-interface-material (TIM) layer with the IC and the substrate. After heat treatment, the TIM contains more than 99 percent of pure silver with only a small amount of organic matter. No volatile organic compounds would be generated after a long term of use. No intermetallic compounds would be generated while the stability under high temperature is obtained. Consequently, embrittlement owing to procedure temperature is dismissed.

An optoelectronic component includes a substrate, a connecting element applied on the substrate and a layer sequence that emits electromagnetic radiation. The layer sequence is applied on the connecting element. The connecting element includes at least one connecting material that has an oriented molecular configuration. The connecting element has at least one parameter that is anisotropic.

A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations.

A packaging structure and a packaging method are provided. The packaging structure includes a carrier semiconductor structure including a carrier substrate, a carrier dielectric layer, and a carrier top conductive layer inside the carrier dielectric layer and having a top exposed by the carrier dielectric layer. The packaging structure also includes a top semiconductor structure including a top substrate, a first dielectric layer, a zeroth conductive layer, and a second dielectric layer, wherein a position of the zeroth conductive layer corresponds to a position of the carrier top conductive layer. Further, the packaging structure includes a conductive plug formed on one side of the zeroth conductive layer, and penetrating through the top substrate, the first dielectric layer, and the second dielectric layer, wherein the conductive plug is electrically connected to each of the zeroth conductive layer and the carrier top conductive layer.

A batch soldering method includes providing a first passive device, arranging the first passive device on a first metal region of a substrate with a region of first solder material between the first passive device and the substrate, providing a semiconductor die, arranging the semiconductor die on a second metal region of the substrate with a region of second solder material between the semiconductor die and the substrate, and performing a common soldering step that simultaneously forms a first soldered joint from the region of first solder material and forms a second soldered joint from the region of second solder material. The common soldering step is performed at a soldering temperature such that one or more intermetallic phases form within the second soldered joint, each of the one or more intermetallic phases having a melting point above the second solder material and the soldering temperature.

A method for fabricating semiconductor die with die-attach preforms is disclosed. In embodiments, the method includes: applying an uncured die-attach paste material to a surface of a forming substrate to form one or more die-attach preforms, the surface of the forming substrate formed from a hydrophobic material; curing the one or more die-attach preforms; performing one or more planarization processes on the one or more die-attach preforms; coupling a first surface of a semiconductor die to a handling tool; and bonding a second surface of the semiconductor die to at least one die-attach preform of the one or more die-attach preforms.

A device manufacturing method includes: applying a bonding material in a predetermined position on a mounting face of a base by dispensing the bonding material through a nozzle of a bonding machine, in which an outline of a leading end face of the nozzle defines an area of at least 75% of a bonding face of a component to be mounted, so that the bonding material applied onto the mounting face has an outline that at least partially extends beyond a shape of the bonding face; and bonding the bonding face in the predetermined position on the mounting face by placing and pressing the component onto the base via the bonding material so that at least a portion of the bonding material interposed between the mounting face of the base and the bonding face of the component flows out beyond the bonding face of the component.

This member connection method includes: a cutting step of forming cutting lines C in an adhesive layer at predetermined intervals at least in a width direction of an adhesive tape and making segments of the adhesive layer divided by the cutting lines C continuous at least in a lengthwise direction of the adhesive tape; a transfer step of disposing the segments to face a connection surface of one member to be connected, pressing a heating and pressing tool having an arbitrary pattern shape against the adhesive tape from a separator side and selectively transferring the segments to the one member to be connected; and a connection step for connecting another member to be connected to the one member to be connected via the segments transferred to the one member to be connected.

Interconnecting a first chip and a second chip by a bridge member includes a chip handler for handling the first chip and the second chip. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The chip handler has an opening and at least one support surface for supporting the first surfaces of the first chip and the second chip when the first chip and the second chip are mounted to the chip handler. A chip support member supports the first chip and the second chip from the second surfaces, and a bridge handler is provided for inserting the bridge member through the opening of the chip handler and for placing the bridge member onto the first sets of terminals of the first chip and the second chip.