A semiconductor package includes: a lower package; and an upper package stacked on the lower package, wherein the lower package includes: a first redistribution structure; a semiconductor chip mounted on the first redistribution structure; a first molding layer surrounding the semiconductor chip on the first redistribution structure; and first vertical connection conductors disposed on the first redistribution structure and vertically passing through the first molding layer, wherein the upper package includes: a second molding layer disposed on the lower package; second vertical connection conductors vertically passing through the second molding layer and electrically connected to the first vertical connection conductors; and an antenna structure disposed on the second molding layer.

A vertical type multi-chip device includes a base structure, an intermediate layer, a first functional chip, and a second functional chip. The intermediate layer is disposed on the base structure and has a first signal transmission path and a second signal transmission path. The first functional chip is embedded in the intermediate layer and electrically connected to the base structure. The second functional chip is disposed on the intermediate layer and configured to be electrically connected to the first functional chip via the first signal transmission path and to the base structure via the second signal transmission path.

An electrical package can include a substrate having a first side and a second side opposite the first side. One or more electrical components mounted to the substrate, and a plurality of electrically conductive interconnect members can be coupled to the second side of the substrate. At least one of the interconnect members can have an elongated shape with a length that is longer than a width. The interconnect member with the elongated shape positioned can be at or proximate one of the corners. The interconnect members can be arranged as a grid, with first interconnect members each occupying a single grid cell, and second interconnect members each occupying at least two grid cells. The second interconnect members can have a shape of two of the first interconnect members coupled by a bridge portion.

Disclosed is a semiconductor module comprising a module substrate having a top surface and a bottom surface that are opposite to each other, a plurality of semiconductor packages on the top surface of the module substrate and arranged in a first direction parallel to the top surface of the module substrate, and a clip structure on the top surface of the module substrate and spaced apart from the plurality of semiconductor packages in the first direction. The clip structure includes a body part on the top surface of the module substrate and spaced apart from the plurality of semiconductor packages in the first direction, and a connection part that extends from the body part across a lateral surface of the module substrate onto the bottom surface of the module substrate.

An embedded module according to the present invention includes a base substrate having a multi-layer wiring, at least two semiconductor chip elements having different element thicknesses, each of the semiconductor chip element having a first surface fixed to the base substrate and having a connection part on a second surface, an insulating photosensitive resin layer enclosing the semiconductor chip elements on the base substrate and being formed by a first wiring photo via, a second wiring photo via, and a wiring, the first wiring photo via electrically connected to the connection part of the semiconductor chip elements, the second wiring photo via arranged at the outer periphery of each of the semiconductor chip elements and electrically connected to a connection part of the base substrate, the wiring arranged so as to be orthogonal to and electrically connected to the first wiring photo via and the second wiring photo via.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure also includes a first chip structure and a second chip structure over the substrate. The chip package structure further includes an anti-warpage bar over a first portion of the first chip structure and over a second portion of the second chip structure. A width of the anti-warpage bar overlapping the second portion of the second chip structure is greater than a width of the anti-warpage bar overlapping the first portion of the first chip structure.

A semiconductor package is provided. The semiconductor package may include a first semiconductor die, a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a width smaller than a width of the first semiconductor die, a third semiconductor die stacked on the second semiconductor die, the third semiconductor die having a width smaller than the width of the first semiconductor die, and a mold layer covering side surfaces of the second and third semiconductor dies and a top surface of the first semiconductor die. The second semiconductor die may include a second through via, and the third semiconductor die may include a third conductive pad in contact with the second through via.

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate that includes a chip region and an edge region around the chip region, and a semiconductor chip on the chip region of the redistribution substrate. The redistribution substrate includes a plurality of dielectric layers that are vertically stacked, a plurality of redistribution patterns on the chip region and in each of the dielectric layers, and a redistribution test pattern on the edge region and at a level the same as a level of at least one of the redistribution patterns.

A semiconductor device includes a substrate having cell array and extension regions, a gate electrode structure having gate electrodes stacked in a first direction, a channel through the gate electrode structure on the cell array region, a first division pattern extending in the second direction on the cell array and extension regions, the first division pattern being at opposite sides of the gate electrode structure in a third direction, an insulation pattern structure partially through the gate electrode structure on the extension region, a through via through the insulation pattern structure, and a support layer on the gate electrode structure and extending on the cell array and extension regions, the support layer contacting an upper sidewall of the first division pattern, and the support layer not contacting an upper surface of a portion of the first division pattern on the extension region adjacent to the insulation pattern structure.

A semiconductor package includes a substrate; and a first semiconductor device and a second semiconductor device that are provided on the substrate. The substrate includes a first dielectric layer and a second dielectric layer provided on the first dielectric layer, a plurality of signal lines provided between the first dielectric layer and the second dielectric layer and connecting the first semiconductor device to the second semiconductor device, and a conductive pad and a conductive plate provided on the second dielectric layer. The conductive pad overlaps the first semiconductor device or the second semiconductor device. The conductive plate overlaps the signal lines.