A semiconductor package includes a semiconductor die, a first thermal conductive pattern and a second thermal conductive pattern. The semiconductor die is encapsulated by an encapsulant. The first thermal conductive pattern is disposed aside the semiconductor die in the encapsulant. The second thermal conductive pattern is disposed over the semiconductor die, wherein the first thermal conductive pattern is thermally coupled to the semiconductor die through the second thermal conductive pattern and electrically insulated from the semiconductor die.

A power conversion device includes a plurality of semiconductor modules, a plurality of coolers, and a frame. The frame pressurizes and holds a stacked body in which the semiconductor modules and the coolers are alternately stacked. The frame includes a first frame and a second frame that sandwich the stacked body therebetween. The first frame is a plate material bent to surround the stacked body from three directions, and includes a pair of side walls extending in the stacking direction of the stacked body, and an abutting wall extending between the side walls and abutting the stacked body. The abutting wall is bent outward from the frame. Each of the side walls is bent inward from the frame.

A package includes an integrated circuit. The integrated circuit includes a first chip, a second chip, a third chip, and a fourth chip. The second chip and the third chip are disposed side by side on the first chip. The second chip and the third chip are hybrid bonded to the first chip. The fourth chip is fusion bonded to at least one of the second chip and the third chip.

Disclosed embodiments include frame-array interconnects that have a ledge portion to accommodate a passive device. A seated passive device is between at least two frame-array interconnects for semiconductor package-integrated decoupling capacitors.

An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

A semiconductor package device includes a first semiconductor package, a second semiconductor package, and first connection terminals between the first and second semiconductor packages. The first semiconductor package includes a lower redistribution substrate, a semiconductor chip, and an upper redistribution substrate vertically spaced apart from the lower redistribution substrate across the semiconductor chip. The upper redistribution substrate includes a dielectric layer, redistribution patterns vertically stacked in the dielectric layer and each including line and via parts, and bonding pads on uppermost redistribution patterns. The bonding pads are exposed from the dielectric layer and in contact with the first connection terminals. A diameter of each bonding pad decreases in a first direction from a central portion at a top surface of the upper redistribution substrate to an outer portion at the top surface thereof. A thickness of each bonding pad increases in the first direction.

Disclosed are redistribution substrates and semiconductor packages including the same. For example, a redistribution substrate including a dielectric pattern, and a first redistribution pattern in the dielectric pattern is provided. The first redistribution pattern may include: a first via part having a first via seed pattern and a first via conductive pattern on the first via seed pattern, and a first wiring part having a first wiring seed pattern and a first wiring conductive pattern, the first wiring part being disposed on the first via part and having a horizontal width that is different from a horizontal width of the first via part. Additionally, the first wiring seed pattern may cover a bottom surface and a sidewall surface of the first wiring conductive pattern, and the first via conductive pattern is directly connected to the first wiring conductive pattern.

A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.

A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.

Disclosed are apparatus comprising a substrate and techniques for fabricating the same. The substrate may include a first metal layer having signal interconnects on a first side of the substrate. A second metal layer may include ground plane portions on a second side of the substrate. Conductive channels may be formed in the substrate and coupled to the ground plane portions. The conductive channels are configured to extend the ground plane portions towards the signal interconnects to reduce a distance from individual signal interconnects to individual conductive channels. The distance may be in a range of seventy-five percent to fifty percent of a substrate thickness between the first metal layer and the second metal layer.