A first wafer, a method of fabricating thereof and a wafer stack are disclosed. The first wafer includes a first substrate, a first dielectric layer on the first substrate, first metal layers embedded in the first dielectric layer, first switching holes extending partially through the first dielectric layer and exposing the first metal layers, a first interconnection layer filling up the first switching holes and electrically connected to the first metal layers, a first insulating layer residing on surfaces of both the first dielectric layer and the first interconnection layer, first contact holes extending through the first insulating layer and exposing the first interconnection layer, and a second interconnection layer filling up the first contact holes and electrically connected to the first interconnection layer. Filling the first contact holes and the first switching holes with different interconnection layers reduces the difficulty in fabricating interconnection structures for the first metal layers.

Composite materials including a thin-film layer of lateral p-n junctions can be employed in circuits or various components of electrical devices. A composite material comprises a thin-film layer including p-type regions alternating with n-type regions along a face of the thin-film layer, the p-type regions comprising electrically conductive particles dispersed in a first organic carrier and the n-type regions comprising electrically conductive particles dispersed in a second organic carrier, wherein p-n junctions are established at interfaces between the p-type and n-type regions.

Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch.

A power module includes a number of sub-modules connected via removable jumpers. The removable jumpers allow the connections between one or more power semiconductor die in the sub-modules to be reconfigured, such that when the removable jumpers are provided, the power module has a first function, and when the removable jumpers are removed, the power module has a second function. The removable jumpers may also allow for independent testing of the sub-modules. The power module may also include a multi-layer printed circuit board (PCB), which is used to connect one or more contacts of the power semiconductor die. The multi-layer PCB reduces stray inductance between the contacts and therefore improves the performance of the power module.

We disclose herein a semiconductor device sub-assembly comprising: a plurality of semiconductor units laterally spaced to one another; a semiconductor unit locator comprising a plurality of holes, wherein each semiconductor unit is located in each hole of the semiconductor unit locator; a plurality of pressure means for applying pressure to each semiconductor unit, and a conductive malleable layer located between the plurality of pressure means and the semiconductor unit locator.

A power semiconductor module includes a plurality of power semiconductor chips. A housing accommodates the power semiconductor chips. A first module electrode on a first side of the housing electrically is connected to a first chip electrode of the power semiconductor chips. A second module electrode on a second side of the housing electrically is connected to a second chip electrode. A surge arrester arrangement with a surge arrester is accommodated in the housing such that a first electrode of the surge arrester arrangement is provided at the first side of the housing and a second electrode of the surge arrester arrangement is provided at the second side of the housing. The power semiconductor chips are arranged in an annular region in the housing and the surge arrester arrangement is arranged within the annular region.

A high peak bandwidth I/O channel embedded within a multilayer surface interface that forms the bus circuitry electrically interfacing the output or input port on a first semiconductor die with the input or output port on a second semiconductor die.

A power module (PM) includes: an insulating substrate; a semiconductor device disposed on the insulating substrate, the semiconductor device including electrodes on a front surface side and a back surface side thereof; and a graphite plate having an anisotropic thermal conductivity, the graphite plate of which one end is connected to the front surface side of the semiconductor device and the other end is connected to the insulating substrate, wherein heat of the front surface side of the semiconductor device is transferred to the insulating substrate through the graphite plate. There is provide an inexpensive power module capable of reducing a stress and capable of exhibiting cooling performance not inferior to that of the double-sided cooling structures.

A diode pack housing for a rotating rectifier assembly can include a body having an interior surface defining an interior cavity open on a first end and configured to contain a diode pack and a plurality of bus bar channels defined axially on or in the inner surface in the interior cavity. The plurality of bus bar channels can be five or less bus bar channels.

A semiconductor structure includes an insulating encapsulant, a semiconductor element, a redistribution layer and an insulating layer. The semiconductor element is embedded in the insulating encapsulant. The redistribution layer is disposed over the insulating encapsulant and electrically connected to the semiconductor element. The insulating layer is disposed in between the insulating encapsulant and the redistribution layer, wherein an uneven interface exists between the insulating layer and the insulating encapsulant, and a planar interface exists between the insulating layer and the redistribution layer.