Disclosed are a composition for depositing a thin film including an organometallic compound including strontium, barium, or a combination thereof; and at least one unshared electron pair-containing compound represented by Chemical Formula 1, a method of manufacturing a thin film using the composition for depositing the thin film, and the thin film manufactured from the composition for depositing the thin film, and a semiconductor device including the thin film.

Describe is a resonator that uses ferroelectric (FE) material in a capacitive structure. The resonator includes a first plurality of metal lines extending in a first direction; an array of capacitors comprising ferroelectric material; a second plurality of metal lines extending in the first direction, wherein the array of capacitors is coupled between the first and second plurality of metal lines; and a circuitry to switch polarization of at least one capacitor of the array of capacitors. The switching of polarization regenerates acoustic waves. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using metal lines above and adjacent to the FE based capacitors.

A metal-insulator-metal (MIM) capacitor includes a first group of metal contacts disposed on a first region of an isolation layer spaced apart from each other in a first direction, a second group of metal contacts disposed on a second region of the isolation layer spaced apart from each other in the first direction, a dielectric layer disposed between the first group of metal contacts and the second group of metal contacts, a first metal electrode disposed to contact the top surfaces of the first group of metal contacts, and a second metal electrode disposed to contact the top surfaces of the second group of metal contacts.

A capacitor that includes a lower electrode; a dielectric film; an upper electrode; a first protective film that has a first through hole that opens to the upper electrode and a second through hole that opens to the lower electrode, and has a first upper surface; a second protective film that has a second upper surface located higher than the first upper surface of the first protective film; a first terminal electrode electrically connected to the upper electrode through the first through hole, and extends to at least the second upper surface of the second protective film; and a second terminal electrode electrically connected to the lower electrode through the second through hole, and extends to at least the second upper surface of the second protective film.

Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer

Disclosed are a semiconductor device and a semiconductor memory device including the same. A semiconductor device may include a first electrode, a second electrode on the first electrode, a ferroelectric layer between the first electrode and the second electrode, an anti-ferroelectric layer in contact with the ferroelectric layer, and an insertion layer spaced apart from the ferroelectric layer and in contact with the anti-ferroelectric layer.

Various embodiments of the present disclosure are directed towards a ferroelectric random-access memory (FeRAM) cell or some other suitable type of memory cell comprising a bottom-electrode interface structure. The memory cell further comprises a bottom electrode, a switching layer over the bottom electrode, and a top electrode over the switching layer. The bottom-electrode interface structure separates the bottom electrode and the switching layer from each other. Further, the interface structure is dielectric and is configured to block or otherwise resist metal atoms and/or impurities in the bottom electrode from diffusing to the switching layer. By blocking or otherwise resisting such diffusion, leakage current may be decreased. Further, endurance of the memory cell may be increased.

An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.

An integrated circuit device includes a capacitor structure, wherein the capacitor structure includes: a bottom electrode over a substrate; a supporter on a sidewall of the bottom electrode; a dielectric layer on the bottom electrode and the supporter; and a top electrode on the dielectric layer and covering the bottom electrode. The bottom electrode comprises: a base electrode layer over the substrate and extending in a first direction that is perpendicular to a top surface of the substrate, and a conductive capping layer including niobium nitride that is between a sidewall of the base electrode layer and the dielectric layer, and also between a top surface of the base electrode layer and the dielectric layer.