A semiconductor device includes a capacitor. The capacitor includes a bottom electrode, a dielectric layer, and a top electrode that are sequentially stacked in a first direction. The dielectric layer includes a first dielectric layer and a second dielectric layer that are interposed between the bottom electrode and the top electrode and are stacked in the first direction. The first dielectric layer is anti-ferroelectric, and the second dielectric layer is ferroelectric. A thermal expansion coefficient of the first dielectric layer is greater than a thermal expansion coefficient of the second dielectric layer.

A semiconductor device includes a transistor disposed on a substrate; and a capacitor structure electrically connected to the transistor, wherein the capacitor structure includes a first electrode; a dielectric layer structure disposed on the first electrode; and a second electrode disposed on the dielectric layer structure, the dielectric layer structure includes an interfacial layer disposed on the first electrode; a first dielectric layer disposed on the interfacial layer and including any one of a ferroelectric material, an antiferroelectric material, and a combination of a ferroelectric material and an antiferroelectric material; an insertion layer disposed on the first dielectric layer; and a second dielectric layer disposed on the insertion layer and including a paraelectric material.

Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

A semiconductor device includes: a first electrode; a second electrode; and a dielectric layer stack positioned between the first electrode and the second electrode, the dielectric layer stack including a first anti-ferroelectric layer, a second anti-ferroelectric layer, and a ferroelectric layer between the first anti-ferroelectric layer and the second anti-ferroelectric.

A ferroelectric thin-film structure includes at least one first atomic layer and at least one second atomic layer. The first atomic layer includes a first dielectric material that is based on an oxide, and the second atomic layer includes both the first dielectric material and a dopant that has a bandgap greater than a bandgap of the dielectric material.

A semiconductor device according to an embodiment of the present disclosure includes a substrate, a first epitaxial electrode layer disposed on the substrate, a ferroelectric epitaxial layer disposed on the first epitaxial electrode layer, a dielectric epitaxial layer disposed on the ferroelectric epitaxial layer, and a second epitaxial electrode layer disposed on the dielectric epitaxial layer. The ferroelectric epitaxial layer implements a negative capacitance. Each of the first and second epitaxial electrode layers includes conductive pyrochlore oxide. The ferroelectric epitaxial layer and the dielectric epitaxial layer are electrically connected in series is non-ferroelectric. A dielectric structure comprising the ferroelectric epitaxial layer and the dielectric epitaxial layer is non-ferroelectric.

In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a bottom electrode layer over a substrate and forming a seed layer over the bottom electrode layer. A ferroelectric switching layer is formed over the bottom electrode layer and to contact the seed layer. The ferroelectric switching layer is formed to have a first region with a first crystal phase and a second region with a different crystal phase. A top electrode layer is formed over the ferroelectric switching layer. One or more patterning processes are performed on the bottom electrode layer, the seed layer, the ferroelectric switching layer, and the top electrode layer to form a ferroelectric random access memory (FeRAM) device.

Provided are dielectric thin-film structures and electronic devices including the same. The dielectric thin-film structure includes a substrate, and a dielectric layer provided on the substrate. The dielectric layer including a tetragonal crystal structure, and crystal grains including a proportion of the crystal grains preferentially oriented such that at least one of a <hk0>, <h00>, or <0k0> direction of a crystal lattice is parallel to or forms an angle of less than 45 degrees an out-of-plane orientation.

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer

Embodiments of semiconductor devices and methods for forming the same are disclosed. In an example, a semiconductor device includes at least one dielectric layer pair including a first dielectric layer and a second dielectric layer different from the first dielectric layer, an interlayer dielectric (ILD) layer in contact with the at least one dielectric layer pair, and one or more capacitors each extending vertically through the ILD layer and in contact with the at least one dielectric layer pair.