A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

Various aspects relate to a memory cell including: a thermally insulating layer disposed over one or more metallization layers of a metallization; an embedding structure disposed over the thermally insulating layer; and a spontaneously polarizable capacitor structure disposed at least partially within the embedding structure, wherein the spontaneously polarizable capacitor structure comprises a spontaneously polarizable memory element; wherein the thermally insulating layer is configured as a heat barrier to reduce a heat transfer through the embedding structure into the one or more metallization layers.

A semiconductor device includes a lower electrode, a ferroelectric film on the lower electrode, an upper electrode on the ferroelectric film, and a first insulating film covering a surface and a side of the upper electrode, a side of the ferroelectric film, and a side of the lower electrode. The first insulating film includes a first opening that exposes a portion of the surface of the upper electrode. A second insulating film covers the first insulating film and includes a second opening that exposes the portion of the surface of the upper electrode through a second opening. A barrier metal is formed in the first opening and the second opening, and is connected to the upper electrode. A connection region in which a material of the barrier metal interacts with a material of the upper electrode extends below an upper-most surface of the upper electrode.

A semiconductor device includes a first electrode, a ferroelectric layer disposed on the first electrode, a dielectric layer disposed on the ferroelectric layer, charge trap sites disposed in an inner region of the dielectric layer, and a second electrode disposed on the dielectric layer. The dielectric layer may have a non-ferroelectric property. The dielectric layer and the ferroelectric layer are disposed between the first electrode and the second electrode and connected in series to each other. The semiconductor device may include charge trap sites distributed in an inner region of the dielectric layer having a non-ferroelectric property.

A semiconductor device and a manufacturing method for the same are provided in such a manner that the oxygen barrier film and the conductive plug in the base of a capacitor are prevented from being abnormally oxidized. A capacitor is formed by layering a lower electrode, a dielectric film including a ferroelectric substance or a high dielectric substance, and an upper electrode in this order on top of an interlayer insulation film with at least a conductive oxygen barrier film in between, and at least a portion of a side of the conductive oxygen barrier film is covered with an oxygen entering portion or an insulating oxygen barrier film.

Disclosed is a capacitor having a high dielectric constant and low leakage current and a method for fabricating the same wherein the capacitor may include a first conductive layer a second conductive layer, a dielectric layer stack between the first conductive layer and the second conductive layer, a dielectric interface layer between the dielectric layer stack and the second conductive layer, and a high work function interface layer between the dielectric interface layer and the second conductive layer.

The present disclosure relates to an integrated chip including a first ferroelectric layer over a substrate. A first electrode layer is over the substrate and on a first side of the first ferroelectric layer. A second electrode layer is over the substrate and on a second side of the first ferroelectric layer, opposite the first side. A first barrier layer is between the first ferroelectric layer and the first electrode layer. A bandgap energy of the first barrier layer is greater than a bandgap energy of the first ferroelectric layer.

According to various aspects, a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory structure disposed between the first electrode and the second electrode, the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode includes: a first electrode layer including a first material having a first microstructure; a functional layer in direct contact with the first electrode layer; and a second electrode layer in direct contact with the functional layer, the second electrode layer including a second material having a second microstructure different from the first microstructure.

Disclosed is a capacitor having a high dielectric constant and low leakage current and a method for fabricating the same, wherein the capacitor may include a first conductive layer, a second conductive layer, a dielectric layer stack between the first conductive layer and the second conductive layer, a dielectric interface layer between the dielectric layer stack and the second conductive layer, and a high work function interface layer between the dielectric interface layer and the second conductive layer.

A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.