An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.

A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.

A metal-insulator-metal (MIM) capacitor includes a first group of metal contacts disposed on a first region of an isolation layer spaced apart from each other in a first direction, a second group of metal contacts disposed on a second region of the isolation layer spaced apart from each other in the first direction, a dielectric layer disposed between the first group of metal contacts and the second group of metal contacts, a first metal electrode disposed to contact the top surfaces of the first group of metal contacts, and a second metal electrode disposed to contact the top surfaces of the second group of metal contacts.

Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region.

A semiconductor device includes a first electrode; a second electrode which is apart from the first electrode; and a dielectric layer between the first electrode and the second electrode. The dielectric layer may include a base material including an oxide of a base metal, the base material having a dielectric constant of about 20 to about 70, and co-dopants including a Group 3 element and a Group 5 element. The Group 3 element may include Sc, Y, B, Al, Ga, In, and/or Tl, and the Group 5 element may include V, Nb, Ta, N, P, As, Sb, and/or Bi.

Provided is a fluorite-based material thin film including an orthorhombic crystal structure having a symmetric segment and a non-symmetric segment; and at least two domains having different polarization directions. At least one of, the symmetric segment is not present at a wall between the domains, or at least two symmetric segments are consecutive. Also provided is a semiconductor device including the fluorite-based material thin film having an orthorhombic crystal structure. A polarization direction of the fluorite-based material thin film is configured to be changed by a structural transition between the symmetric segment and the non-symmetric segment.

A capacitor is provided that includes an electrostatic capacitance forming portion with a first electrode/dielectric layer/second electrode structure, and a silicon portion. Moreover, the silicon portion is disposed on at least a part of a side of the electrostatic capacitance forming portion. When the capacitor is viewed in a thickness direction thereof, a region occupied by the silicon portion in a lower portion of the electrostatic capacitance forming portion is 50% or less.

Provided is a method of preparing a dielectric film having a nanoscale three-dimensional shape and including an oxide, the oxide represented by R.sub.AM.sub.BO.sub.C where R is a divalent element and M is a pentavalent element, the method may include synthesizing a target material, the target material including the divalent element and the pentavalent element; and forming the oxide by depositing the divalent element and the pentavalent element, from the target material, onto a substrate such that the oxide includes a perovskite-type crystal structure, 1.3<B/A<1.7, and 9.0≤C<10.0.

The present disclosure describes a semiconductor device having a ferroelectric memory with improved retention after cycling (RAC) memory window (MW) performance. The semiconductor device includes an interconnect structure on a substrate, a first electrode on the interconnect structure, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer. The first electrode includes a metal nitride conductive material having a nitrogen concentration greater than a metal concentration. The ferroelectric layer includes a ferroelectric material. The second electrode includes the metal nitride conductive material.

The present disclosure relates to a memory device, and more particularly, to a memory device including a substrate, a plurality of vertical structures disposed on the substrate and including insulation layers and lower electrodes, which are alternately laminated with each other, wherein the vertical structures are aligned in a first direction parallel to a top surface of the substrate and a second direction crossing the first direction, an upper electrode disposed on a top surface and side surfaces of each of the vertical structures, and a first dielectric layer disposed between the upper electrode and the vertical structures to cover the top surface and the side surfaces of each of the vertical structures. Here, the first dielectric layer includes a ferroelectric material.