A semiconductor device includes a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: electrodes including one or more first electrodes and one or more second electrodes; and one or more insulating layers disposed between adjacent electrodes. The MIM capacitor is disposed in an interlayer dielectric (ILD) layer disposed over a substrate. The one or more first electrodes are connected to a side wall of a first via electrode disposed in the ILD layer, and the one or more second electrodes are connected to a side wall of a second via electrode disposed in the ILD layer. In one or more of the foregoing or following embodiments, the one or more insulating layers include a high-k dielectric material.

Disclosed is an oxide electrode for a device including a top electrode, a bottom electrode, and a polarizable material layer interposed between the top electrode and the bottom electrode. An oxide electrode is used as the bottom electrode unlike the top electrode.

An integrated circuit device includes: a lower electrode disposed on a substrate; an insulating support pattern supporting the lower electrode; a dielectric film surrounding the lower electrode and the insulating support pattern; a high-k interface layer arranged between the lower electrode and the dielectric film and between the insulating support pattern and the dielectric film, wherein the high-k interface layer contacts the insulating support pattern and includes a zirconium oxide layer; and an upper electrode disposed adjacent the lower electrode, wherein the high-k interface layer and the dielectric film are disposed between the upper electrode and the lower electrode.

A method for forming a double-sided capacitor structure includes: providing a base, the base including a substrate, a plurality of capacitor contacts located in the substrate, a stack structure located on a surface of the substrate and a plurality of capacitor holes running through the stack structure and exposing the capacitor contacts, the stack structure including sacrificial layers and support layers which are stacked alternately; successively forming a first electrode layer, a first dielectric layer and a second electrode layer on inner walls of the capacitor holes; forming a first conductive filling layer in the capacitor holes; forming an auxiliary layer for sealing the capacitor holes; removing a part of the auxiliary layers and several of the support layers and the sacrificial layers to expose the first electrode layer; and, forming a second dielectric layer and a third electrode layer.

A capacitor unit formed by a capacitor integrated structure is provided. The capacitor integrated structure is cut to form capacitor units separated from each other, and each of the capacitor units includes: a substrate; an isolation layer located on the substrate; a capacitor stacked structure located on the isolation layer, wherein the isolation layer electrically isolates the substrate from the capacitor stacked structure; and two electrode connectors located on the capacitor stacked structure and being exposed.

A deep trench is formed in a substrate, and a layer stack including at least three metallic electrode plates interlaced with at least two node dielectric layers is formed in, and over, the deep trench. A contact-level dielectric material layer over the layer stack, and contact via cavities are formed therethrough. The depths of the contact via cavities are differentiated by selectively increasing the depth of a respective subset of the contact via cavities by performing at least twice a combination of processing steps that includes an etch mask formation process and an etch process. A combination of a dielectric contact via liner and a plate contact via structure can be formed within each of the contact via cavities. Plate contact via structures that extend through any metallic electrode plate can be electrically isolated from such a metallic electrode plate by a respective dielectric contact via liner.

Provided are a semiconductor MIM capacitor device and a method for manufacturing the same. The method includes: providing a substrate, and sequentially forming a bottom electrode layer and a first dielectric layer over the substrate; performing patterning on the first dielectric layer by applying a first mask to form a through hole for the MIM-capacitor disposed in the MIM-capacitor region and through holes for the conductive-plugs disposed in the non-MIM-capacitor region; sequentially forming an interconnection metal layer and a second dielectric layer; performing a surface planarization treatment to remove parts of the interconnection metal layer and the second dielectric layer that are outside the through hole of MIM-capacitor and the conductive plugs; and forming an upper metal layer by applying a second mask on surfaces of the second dielectric layer of the through holes of MIM-capacitor and the conductive plugs.

An OTP memory capacitor structure includes a semiconductor substrate, a bottom electrode, a capacitor insulating layer and a metal electrode stack structure. The bottom electrode is provided on the semiconductor substrate. The capacitor insulating layer is provided on the bottom electrode. The metal electrode stack structure includes a metal layer, an insulating sacrificial layer and a capping layer stacked in sequence. The metal layer is provided on the capacitor insulating layer and is used as a top electrode. The insulating sacrificial layer is provided between the metal layer and the capping layer. A manufacturing method of the OTP memory capacitor structure is also provided. By the provision of the insulating sacrificial layer, the bottom electrode formed first can be prevented from being damaged by subsequent etching and other processes, so that the OTP memory capacitor structure has better electrical characteristics.

A capacitor includes a lower electrode including a perovskite material, an upper electrode spaced apart from the lower electrode, a dielectric layer positioned between the lower electrode and the upper electrode and including a perovskite material, and a passivation layer positioned between the lower electrode and the dielectric layer and including Sr.sub.xTi.sub.yO.sub.3 in which a content of Ti is greater than a content of Sr.

A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.