A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

A capacitor includes a lower electrode including a first metal material and having a first crystal size in a range of a few nanometers, a dielectric layer covering the lower electrode and having a second crystal size that is a value of a crystal expansion ratio times the first crystal size and an upper electrode including a second metal material and covering the dielectric layer. The upper electrode has a third crystal size smaller than the second crystal size.

A HfO2-based ferroelectric capacitor and a preparation method therefor, and a HfO2-based ferroelectric memory, relating to the technical field of microelectronics. The purpose of enlarging the memory window of the ferroelectric memory is achieved by inserting an Al.sub.2O.sub.3 intercalation layer having a coefficient of thermal expansion smaller than TiN between a dielectric layer and an upper electrode (TiN) of the ferroelectric capacitor. The HfO.sub.2-based ferroelectric capacitor comprises a substrate layer, a lower electrode, a dielectric layer, an Al.sub.2O.sub.3 intercalation layer, an upper electrode and a metal protection layer from bottom to top. The memory window can be increased, information misreading is effectively prevented, and therefore, the reliability of the memory is improved.

The present disclosure provides a method of forming a capacitor hole, and a semiconductor structure. The method includes: providing a substrate, where an electrode is formed in the substrate; forming a pattern definition layer on a surface of the substrate; sequentially forming three sets of trenches in the pattern definition layer, where the three sets of trenches intersect with each other at 120°, and a hexagonal hole is formed at an intersection position in the pattern definition layer; etching the substrate along the hexagonal hole by the pattern definition layer as a mask, to form a capacitor hole in the substrate, where a bottom of the capacitor hole is round under a loading effect of etching, and the electrode is exposed at the bottom of the capacitor hole.

A metal-insulator-metal (MIM) capacitor of a semiconductor device and a manufacturing method thereof are provided. The MIM capacitor includes: a first inter metal dielectric layer disposed on a substrate; a plurality of lower electrodes disposed on the first inter metal dielectric layer; a plurality of opening areas respectively disposed between the plurality of lower electrodes; a dielectric layer which covers the plurality of lower electrodes and the plurality of opening areas; and an upper electrode disposed on the dielectric layer. The dielectric layer is in contact with side surfaces and top surfaces of the plurality of lower electrodes. The dielectric layer is in direct contact with the first inter metal dielectric layer.

A capacitor includes: a bottom electrode; a top electrode over the bottom electrode; a dielectric film between the bottom electrode and the top electrode; and a doped Al.sub.2O.sub.3 film between the top electrode and the dielectric film, wherein the doped Al.sub.2O.sub.3 film includes a first dopant, and an oxide including the same element as the first dopant has a higher dielectric constant than a dielectric constant of Al.sub.2O.sub.3.

A semiconductor device including a substrate, lower electrodes disposed on the substrate, at least one support layer in contact with the lower electrodes, a dielectric layer disposed on the lower electrodes, an upper electrode disposed on the dielectric layer, a first interfacial film between the lower electrodes and the dielectric layer, and a second interfacial film between the upper electrode and the dielectric layer. At least one of the first and second interfacial films includes a plurality of layers, wherein the plurality of layers include a first metal element, and a second metal element, and at least one of oxygen \and nitrogen. The lower electrodes include the first metal element. A first region of the first interfacial film includes the second metal element at a first concentration and a second region of the first interfacial film includes the second metal element at a second concentration different from the first concentration.

A capacitor structure, a semiconductor memory device including the same, a method for fabricating the same, and a method for fabricating a semiconductor device including the same are provided. The capacitor structure includes a lower electrode, an upper electrode, and a capacitor dielectric film which is interposed between the lower electrode and the upper electrode, wherein the lower electrode includes an electrode film including a first metal element, and a doping oxide film including an oxide of the first metal element between the electrode film and the capacitor dielectric film, and the doping oxide film further includes a second metal element including at least one of Group 5 to Group 11 and Group 15 metal elements, and an impurity element including at least one of silicon (Si), aluminum (Al), zirconium (Zr) and hafnium (Hf).

A semiconductor device includes a first conductive material, a dielectric structure extending over a top surface of the first conductive material, the dielectric material having a first portion with a first thickness, and a second portion with a second thickness, and a third portion with a third thickness between the first thickness and the second thickness; and a second conductive material extending over the first portion of the dielectric structure. An oxygen-enriched portion of the second conductive material extends along a top surface and a sidewall of the second conductive material. A bottom surface and an interior portion of the second conductive material have an oxygen concentration which is larger than an oxygen concentration of a bottom surface and an interior portion of the second conductive material.

A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.