A semiconductor device includes a plurality of lower electrode structures disposed on a substrate, and a supporter pattern disposed between pairs of lower electrode structures of the plurality of lower electrode structures. The semiconductor device further includes a capacitor dielectric layer disposed on surfaces of each of the plurality of lower electrode structures and the supporter pattern, and an upper electrode disposed on the capacitor dielectric layer. The plurality of lower electrode structures includes a first lower electrode and a second lower electrode disposed on the first lower electrode and having a cylindrical shape. The first lower electrode has a pillar shape. The first lower electrode includes an insulating core. The insulating core is disposed in the first lower electrode. An outer side surface of the first lower electrode and an outer side surface of the second lower electrode are coplanar.

Methods, apparatuses, and systems related to trim a semiconductor structure using oxygen are described. An example method includes forming a support structure for a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming an opening through the semiconductor structure. The method further includes depositing an electrode material within the opening. The method further includes removing portions of the support structure. The method further includes performing a controlled oxidative trim to an upper portion of the electrode material.

A semiconductor device including one or more switches on a substrate, a first electrode connected to the one or more switches and having a helical shape defining a spiral groove, a support in contact with the first electrode, the spiral groove extending between the support and a portion of the first electrode, a capacitor dielectric layer in contact with the first electrode, and a second electrode in contact with the capacitor dielectric layer.

Methods, apparatuses, and systems related to trim a semiconductor structure using oxygen are described. An example method includes forming a support structure for a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming an opening through the semiconductor structure. The method further includes depositing an electrode material within the opening. The method further includes removing portions of the support structure. The method further includes performing a controlled oxidative trim to an upper portion of the electrode material.

A display panel and fabrication method, and a display device are provided. The display panel includes a base substrate, a first transistor and a storage capacitor. The storage capacitor includes a first electrode and a second electrode, and the first electrode and a gate of the first transistor have an overlapped region. The display panel also includes a first insulating layer having a plurality of first vias in the overlapped region, and the first electrode is electrically connected to the gate of the first transistor through the plurality of first vias. A plurality of grooves are formed on a side of the first electrode facing away from the base substrate. A plurality of protrusions are formed on a side of the second electrode facing toward the base substrate. A groove, a protrusion and a first via overlap in a direction perpendicular to the surface of the base substrate.

A capacitor having a substrate, a first electrode layer, a dielectric layer, a second electrode layer, and first and second outer electrodes. The substrate has a first main surface and a second main surface opposite to the first main surface. The first electrode layer is on the first main surface of the substrate. The dielectric layer is on at least part of the first electrode layer. The second electrode layer is on at least part of the dielectric layer. The first outer electrode is electrically connected to the first electrode layer and the second outer electrode is electrically connected to the second electrode layer. At least one of the first electrode layer and the first outer electrode and the second electrode layer and the second outer electrode are in contact with each other at a first contact surface. The first contact surface includes a first uneven surface portion.

The present application provides a memory device having laterally extending capacitors of different lengths and levels. The memory device includes a semiconductor substrate; a first insulating layer disposed over the semiconductor substrate; a first bottom electrode disposed over the first insulating layer; a first dielectric layer disposed over the first bottom electrode; a first recess extending through the first dielectric layer; a first capacitor dielectric conformal to the first recess and in contact with the first bottom electrode; and a first top electrode disposed within the first recess and surrounded by the first capacitor dielectric, wherein the first capacitor dielectric and the first top electrode extend laterally over the first bottom electrode and the semiconductor substrate.

The present disclosure provides a semiconductor structure and a production method thereof so that a non-linear trench structure can be produced, which can increase a surface area of the trench structure without increasing an aspect ratio and maintaining the same footprint. The semiconductor structure includes: a substrate including an upper surface and a lower surface disposed opposite to each other; and at least one trench structure disposed in the substrate and formed downward from the upper surface, where the trench structure is projected on the upper surface to form a first pattern in a curved or broken line shape, and the first pattern includes n second patterns adjacent to each other, and in the n second patterns, odd-numbered second patterns are the same, and even-numbered second patterns are the same, where n is a positive integer.

Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed.