A Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor with implant alignment spacers includes a gate stack comprising a first nitride layer. The first nitride layer is formed on a silicon layer. The gate stack is separated from a substrate by a first oxide layer. The gate stack includes a polysilicon layer formed from the silicon layer, and a second oxide layer is formed on a sidewall of the polysilicon layer. A drain region of the LDMOS transistor is implanted with a first implant aligned to a first edge formed by the second oxide layer. A second nitride layer conformingly covers the second oxide layer. A nitride etch-stop layer conformingly covers the second nitride layer.

A semiconductor device includes a semiconductor part; first and second electrodes respectively on back and front surfaces of the semiconductor part; a control electrode provided inside a trench of the semiconductor part; a third electrode provided inside the trench; a diode element provided at the front surface of the semiconductor part; a resistance element provided on the front surface of the semiconductor part via an insulating film, the diode element being electrically connected to the second electrode; a first interconnect electrically connecting the diode element and the resistance element, the first interconnect being electrically connected to the third electrode; and a second interconnect electrically connecting the resistance element and the semiconductor part. The resistance element is connected in series to the diode element. The diode element is provided to have a rectifying property reverse to a current direction flowing from the resistance element to the second electrode.

A multi-finger high-electron mobility transistor and a method of manufacturing such a transistor, and an electronic device including such a transistor is provided. According to an aspect of the present disclosure, an etching step for reducing donor layer thickness and/or performing an ion implantation is used for locally reducing the 2DEG concentration.

A semiconductor device includes a gate structure extending from a first surface of a semiconductor portion into a mesa section between neighboring field electrode structures and an alignment layer formed on the first surface. The alignment layer includes mask pits formed in the alignment layer in a vertical projection of the field electrode structures. Sidewalls of the mask pits have a smaller tilt angle with respect to the first surface than sidewalls of the field electrode structures. The gate structure is in the vertical projection of a gap between neighboring mask pits.

The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

A power semiconductor device includes an active region and an edge termination region surrounding the active region. A field plate structure arranged around the active region includes at least one electrically conductive track electrically connected to a first potential of a first load terminal at a first joint and, at a second joint, electrically connected to a second potential of a second load terminal. The track forms at least n crossings, wherein n is greater 5, with a straight virtual line that extends from the active region towards an edge of the edge termination region. The difference in potential between adjacent two crossings increases in at least 50% of the length of the virtual line, and/or the difference in potential within, with respect to the active region, the first 20% of the length of virtual line is less than 10% of the total difference in potential along the virtual line.

A semiconductor device includes; a semiconductor substrate; an emitter electrode provided on the semiconductor substrate; a gate electrode provided on the semiconductor substrate; a drift layer of a first conduction type provided in the semiconductor substrate; a source layer of the first conduction type provided on an upper surface side of the semiconductor substrate; a base layer of a second conduction type provided on the upper surface side of the semiconductor substrate; a collector electrode provided below the semiconductor substrate; and a two-part dummy active trench including, at an upper part, an upper dummy part not connected with the gate electrode and including, at a lower part, a lower active part connected with the gate electrode and covered by an insulating film, in a trench of the semiconductor substrate, wherein a longitudinal length of the lower active part is larger than a width of the lower active part.

There is disclosed a structure in a wide band gap material such as silicon carbide wherein there is a buried grid and shields covering at least one middle point between two adjacent parts of the buried grid, when viewed from above. Advantages of the invention include easy manufacture without extra lithographic steps compared with standard manufacturing process, an improved trade-off between the current conduction and voltage blocking characteristics of a JBSD comprising the structure.

A semiconductor device includes a semiconductor layer with a thickness of at most 50 μm. A first metallization structure is disposed on a first surface of the semiconductor layer. The first metallization structure includes a first copper region with a first thickness. A second metallization structure is disposed on a second surface of the semiconductor layer opposite to the first surface. The second metallization structure includes a second copper region with a second thickness.

Structures for suppressing parasitic acoustic waves in semiconductor structures and integrated circuit devices are described. Such integrated circuit devices can, typically, produce undesirable acoustic wave resonances, and the acoustic waves can degrade the performance of the devices. In that context, some embodiments described herein relate to spoiling a conductive path that participates in the generation of acoustic waves. Some embodiments relate to spoiling acoustic characteristics of an acoustic resonant structure that may be present in the vicinity of the device. Combined embodiments that spoil the conductive path and acoustic characteristics are also possible.