A semiconductor device is described. The semiconductor device includes: a Si substrate having a first main surface; a plurality of gate trenches extending from the first main surface into the Si substrate; a semiconductor mesa between adjacent gate trenches; a first interlayer dielectric on the first main surface; a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches; a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts. Methods of producing the semiconductor device are also described.

An integrated circuit (IC) device comprises a high voltage semiconductor device (HVSD) on a frontside of a semiconductor body and further comprises an electrode on a backside of the semiconductor body opposite the frontside. The HVSD may, for example, be a transistor or some other suitable type of semiconductor device. The electrode has one or more gaps directly beneath the HVSD. The one or more gaps enhance the effectiveness of the electrode for improving the breakdown voltage of the HVSD.

A semiconductor device is provided, wherein a semiconductor substrate includes: a first trench portion provided from a front surface of the semiconductor substrate to a predetermined depth, and having a longer portion and a shorter portion as seen from above; and a first conductivity-type floating semiconductor region at least partially exposed on the front surface and surrounded by the first trench portion, an interlayer insulating film has openings to electrically connect an emitter electrode and the floating semiconductor region, the openings include: a first opening closest to an outer end of the floating semiconductor region in a direction parallel to the longer portion; and a second opening second closest to the outer end in the direction parallel to the longer portion, and a distance between the first opening and the second opening is shorter than a distance between any adjacent two of the openings other than the first opening.

A depletion-mode current source having a saturation current of sufficient accuracy for use as a pre-charge circuit in a start-up circuit of an AC-to-DC power converter is fabricated using an enhancement-mode-only process. The depletion-mode current source can be fabricated on the same integrated circuit (IC) as a gallium nitride field-effect transistor (FET) and resistive and capacitive components used in the start-up circuit, without affecting the enhancement-mode-only fabrication process by requiring additional masks or materials, as would be required to fabricate a depletion-mode FET on the same IC as an enhancement-mode FET. The current source includes a resistive patterned two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) channel coupled between two terminals and one or more metal field plates extending from one of the terminals and overlying the patterned area of the channel, the field plates being separated from the channel and from each other by dielectric layers.

A semiconductor Schottky rectifier built in an epitaxial semiconductor layer over a substrate has an anode structure and a cathode structure extending from the surface of the epitaxial layer. The cathode contact structure has a trench structure near the epi-layer and a vertical sidewall surface covered with a gate oxide layer. The cathode structure further comprises a polysilicon element adjacent to the gate oxide layer.

A semiconductor device includes a core gate and a pair of isolation gates. The core gate has a first stack of two or more layers, the first stack including at least (i) a first dielectric layer having a first thickness and (ii) a first electrode layer. The isolation gates are formed on first and second sides of the core gate. The isolation gates are configured to electrically isolate the core gate. At least one of the isolation gates has a second stack of two or more layers, the second stack including at least (i) a second dielectric layer having a second thickness greater than the first thickness and (ii) a second electrode layer.

According to one embodiment, a semiconductor device includes first, second, third electrodes, first, and second semiconductor regions, a first conductive member, and an insulating member. The third electrode is between the first and second electrodes. The first semiconductor region includes first to sixth partial regions. The second semiconductor region includes first to third semiconductor portions. The first conductive member is electrically connected with a first one of the first and third electrodes. The first conductive member includes a first conductive end portion. The insulating member includes first and second nitride regions. The second semiconductor portion is between the fifth partial region and the first nitride region. The third semiconductor portion is between the sixth partial region and the second nitride region. The first nitride region includes a first nitride end portion. The first nitride end portion is in contact with the second semiconductor region.

A semiconductor device includes: a semiconductor substrate including a first surface and a second surface facing each other and including a first semiconductor material; a plurality of fin structures upwardly extending on the first surface of the semiconductor substrate, spaced apart from each other by a plurality of trenches, and including the first semiconductor material as the semiconductor substrate; an insulating layer on the first surface of the semiconductor substrate filling at least a portion of the plurality of trenches; a gate electrode layer between the plurality of fin structures and surrounded by the insulating layer; a first conductive layer covering the plurality of fin structures; a second conductive layer on the second surface of the semiconductor substrate; and a shield layer between the gate electrode layer and the semiconductor substrate, surrounded by the insulating layer, and electrically connected to the second conductive layer.

A High Electron Mobility Transistor (HEMT) having a reduced surface field (RESURF) junction is provided. The HEMT includes a source electrode at a first end and a drain electrode at a second end. A gate electrode is provided between the source electrode and the drain electrode. A reduced surface field (RESURF) junction extends from the first end to the second end. The gate electrode is provided above the RESURF junction. A buried channel layer is formed in the RESURF junction on application of a positive voltage at the gate electrode. The RESURF junction includes an n-type Gallium nitride (GaN) layer and a p-type GaN layer. The n-type GaN layer is provided between the p-type GaN layer and the gate electrode.

A semiconductor device, such as a laterally diffused metal-oxide-semiconductor (LDMOS) transistor, includes a semiconductor substrate in which a source region and a drain region are disposed. The drain region has a drain finger terminating at a drain end. A gate structure is supported by the semiconductor substrate between the source region and the drain region, the gate structure extending laterally beyond the drain end. A drift region in the semiconductor substrate extends laterally from the drain region to at least the gate structure. The drift region is characterized by a first distance between a first sidewall of the drain finger and a second sidewall of the gate structure, and the gate structure is laterally tilted away from the drain region at the drain end of the drain finger to a second distance that is greater than the first distance.