The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a passivation layer covering the first gate conductor, and a second gate conductor disposed on the passivation layer and on a second region of the second nitride semiconductor layer, wherein the first region is laterally spaced apart from the second region.

The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a first source electrode disposed on a first side of the first gate conductor, a first field plate disposed on a second side of the first gate conductor; and a capacitor having a first conductive layer and a second conductive layer and disposed on a second region of the second nitride semiconductor layer. Wherein the first conductive layer of the capacitor and the first source electrode have a first material, and the second conductive layer of the capacitor and the first field plate have a second material.

The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a nitride semiconductor layer disposed on the substrate, a first gate stack in contact with the nitride semiconductor layer, and a resistor laterally spaced apart from the first gate stack and electrically connected to first gate stack. The resistor comprises a first conductive terminal in contact with the nitride semiconductor layer, a second conductive terminal in contact with the nitride semiconductor layer; a first doped region of the nitride semiconductor layer between the first conductive terminal and the second conductive terminal; and a first conductive region of the nitride semiconductor layer in contact with the first conductive terminal and the second conductive terminal.

A semiconductor device includes a semiconductor layer, a source region and a drain region that are formed in the semiconductor layer and at an interval in a first direction, a gate insulating film that is formed such as to cover a channel region between the source region and the drain region, and a gate electrode that is formed on the gate insulating film and opposes the channel region across the gate insulating film. The gate insulating film has a major portion on which the gate electrode is formed and extension portions projecting outward from each of both sides of the major portion in a second direction orthogonal to the first direction and leak current suppressing electrodes are formed on the extension portions.

A semiconductor device includes a gate electrode, first and second passivation layers, first and second field plates. The gate electrode is disposed above nitride-based semiconductor layers. The first passivation layer covers the gate electrode. The first field plate is disposed on the first passivation layer. The first passivation layer has a first portion covered with the first field plate and a second portion free from coverage of the first field plate. The second passivation layer covers the first field plate. The second field plate is disposed over the second passivation layer. The second passivation has a first portion covered with the second field plate and a second portion is free from coverage of the second field plate. A thickness difference between the first and second portions of the first passivation layer is less than a thickness difference between the first and second portions of the second passivation layer.

A method of forming a high electron mobility transistor (HEMT) includes: providing a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate; forming a first insulating layer on the barrier layer; and forming a gate contact, a source contact, and a drain contact on the barrier layer. An interface between the first insulating layer and the barrier layer comprises a modified interface region on a drain access region and/or a source access region of the semiconductor structure such that a sheet resistance of the drain access region and/or the source access region is between 300 and 400 Ω/sq.

A semiconductor protection device includes: an N-type epitaxial layer, a device isolation layer disposed in the N-type epitaxial layer, an N-type drift region disposed below the device isolation layer, an N-type well disposed in the N-type drift region, first and second P-type drift regions, respectively disposed to be in contact with the device isolation layer, and spaced apart from the N-type drift region, first and second P-type doped regions, respectively disposed in the first and second P-type drift regions, first and second N-type floating wells, respectively disposed in the first and second P-type drift regions to be spaced apart from the first and second P-type doped regions, and disposed to be in contact with the device isolation layer, and first and second contact layer, respectively disposed to cover the first and second N-type floating well, to be in contact with the device isolation layer.

A power device includes: a semiconductor layer, a well region, a body region, a gate, a sub-gate, a source, a drain, and an electric field adjustment region. The sub-gate is formed above a top surface of the semiconductor layer, wherein a portion of the well region is located vertically beneath the sub-gate. The sub-gate is not directly connected to the gate. The electric field adjustment region has a conductivity type which is opposite to that of the well region. The electric field adjustment region is formed beneath and not in contact with the top surface of the semiconductor layer. The electric field adjustment region is located in the well region of the semiconductor layer, and at least a portion of the electric field adjustment region is located vertically beneath the sub-gate.

A transistor device according to some embodiments includes a channel layer, a barrier layer on the channel layer, and source and drain contacts on the barrier layer, and a gate contact on the barrier layer between the source and drain contacts. The channel layer includes a sub-layer having an increased doping concentration level relative to a remaining portion of the channel layer. The presence of the sub-layer may reduce drain lag without substantially increasing gate lag.

A semiconductor device includes a layer of a first semiconducting material, where the first semiconducting material is epitaxially grown to have a crystal structure of a first substrate. The semiconductor device further includes a layer of a second semiconducting material disposed adjacent to the layer of the first semiconducting material to form a heterojunction with the layer of the first semiconducting material. The semiconductor device further includes a first component that is electrically coupled to the heterojunction, and a second substrate that is bonded to the layer of the first semiconducting material.