Disclosed herein are IC structures, packages, and devices assemblies that use ions or fixed charge to create field plate structures which are embedded in a dielectric material between gate and drain electrodes of a transistor, ion- or fixed charge-based field plate structures may provide viable approaches to changing the distribution of electric field at a transistor drain to increase the breakdown voltage of a transistor without incurring the large parasitic capacitances associated with the use of metal field plates. In one aspect, an IC structure includes a transistor, a dielectric material between gate and drain electrodes of the transistor, and an ion- or fixed charge-based region within the dielectric material, between the gate and the drain electrodes. Such an ion- or fixed charge-based region realizes an ion- or fixed charge-based field plate structure. Optionally, the IC structure may include multiple ion- or fixed charge-based field plate structures.

The disclosed embodiments include an ESD robust transistor with a compound-SCR protection. The transistor may include a semiconductor substrate having a first conductivity type, a drain region coupled with the semiconductor substrate having a drain SCR component with a first drain region of the first conductivity type and a second drain region of the second conductivity type. The transistor may also include a source coupled with the semiconductor substrate, a channel region of the second conductivity type, and a gate coupled with the channel region having SCR components with a first gate region of the first conductivity type and a second gate region of the second conductivity type. The drain SCR components and the gate SCR components may create a low resistance discharge path along the channel region that activates in response to the ESD such that the ESD discharges through the transistor without causing damage to the transistor.

High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.

An oxide semiconductor device has an improved withstand voltage when an inverse voltage is applied, while suppressing diffusion of different types of materials to a Schottky interface. The oxide semiconductor device includes an n-type gallium oxide epitaxial layer, p-type oxide semiconductor layers of an oxide that is a different material from the material for the gallium oxide epitaxial layer, a dielectric layer formed to cover at least part of a side surface of the oxide semiconductor layer, an anode electrode, and a cathode electrode. Hetero pn junctions are formed between the lower surfaces of the oxide semiconductor layers and a gallium oxide substrate or between the lower surfaces of the oxide semiconductor layers and the gallium oxide epitaxial layer.

A semiconductor device and a method of manufacturing a semiconductor device capable of suppressing breakdown due to current concentration while suppressing an increase in chip size are provided. According to one embodiment, a semiconductor device has a gate resistance on a main surface side of a semiconductor substrate, a first contact and a second contact connected to an upper surface of the gate resistance, and a carrier discharging portion that discharges the carrier formed in the semiconductor substrate below the gate resistance, the gate resistance having a first contacting portion to which a first contact is connected, a second contacting portion to which a second contact is connected, and a plurality of extending portions with one end connected to the first contacting portion and the other end connected to the second contacting portion. The gate resistance forms an opening between adjacent extending portions and the carrier discharge portion is formed in the opening.

The reliability of resistive field plate part-containing semiconductor device is improved. In peripheral region of semiconductor chip, the outer circumference end of internal circulation wire is separated from outer circumference end of first conductor pattern of resistive field plate part toward element region. Inner circumference end of external circulation wire is separated from inner circumference end of second conductor pattern of resistive field plate part toward outer circumference of the chip. First conductor pattern of resistive field plate part is partially extended to over thin insulation film to form first lead-out part, and internal circulation wire and first lead-out part of first conductor pattern are electrically coupled via first coupling hole. Second conductor pattern of resistive field plate part is partially extended to over thin insulation film to form second lead-out part, external circulation wire and second lead-out part of second conductor pattern are electrically coupled via second coupling hole.

A semiconductor structure is provided, which includes a semiconductor device, a first conductive layer, and a gate runner. The semiconductor device includes an upper surface, a gate terminal, a source terminal, and a drain terminal. The first conductive layer is deposited on the upper surface and coupled to the source terminal. The gate runner is overlapped with the first conductive layer and coupled to the gate terminal. The gate runner and the first conductive layer are configured to contribute a parasitic capacitance between the gate terminal and the source terminal.

A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, and first and second cells each configured for controlling a load current and electrically connected to the first load terminal structure and to a drift region. A first mesa in the first cell includes a port region electrically connected to the first load terminal structure, and a first channel region coupled to the drift region. A second mesa included in the second cell includes a port region electrically connected to the first load terminal structure, and a second channel region coupled to the drift region. The mesas are spatially confined in a direction perpendicular to a direction of the load current by an insulation structure, and have a total extension of less than 100 nm in that direction. The first channel region includes an inversion channel. The second channel region includes an accumulation channel.

Disclosed is an insulated gate bipolar transistor (IGBT) power device, including a bipolar transistor, a first MOS transistor, a second MOS transistor, a body diode and a body region contact diode. An anode of the body region contact diode and an anode of the body diode are connected to the bipolar transistor. A first gate of the first MOS transistor is externally connected to a gate voltage of the IGBT power device and configured to control turning on and off of the first MOS transistor by means of the gate voltage of the IGBT power device. A second gate of the second MOS transistor is connected to an emitter voltage of the IGBT power device and configured to control turning on and off of the second MOS transistor by means of the emitter voltage of the IGBT power device.

A power semiconductor transistor includes an electrically conductive contact structure including a plurality of contacts. A first one of the contacts is electrically connected to both a first load terminal and a first zone of a doped semiconductor structure. A second one of the contacts is electrically coupled to one of the first load terminal and a control electrode. The second contact laterally overlaps with both a second zone of the doped semiconductor structure, and a gap is formed between two adjacent field plates. The second zone of the doped semiconductor structure terminates in a section laterally overlapping with the gap.