The application relates to a semiconductor die including a device in an active area of the die. The device includes a field electrode region formed in a field electrode trench extending vertically into a semiconductor body. The field electrode region includes a first and a second field electrode stacked vertically above each other in the field electrode trench. An edge termination structure laterally between the active area and a lateral edge region of the die includes a first and a second shield electrode arranged laterally consecutive between the active area and the lateral edge region to stepwise decrease an electrical potential between the edge region and the active area.

A semiconductor device includes a semiconductor substrate having a major surface and both an element-forming region and an outer peripheral voltage-withstanding region that are provided on the major surface side of the semiconductor substrate. The element-forming region includes both a cell region for forming a power element and a circuit element region for forming at least one circuit element. The circuit element region is interposed between the outer peripheral voltage-withstanding region and the cell region. The outer peripheral voltage-withstanding region includes a boundary region that adjoins the element-forming region. In the boundary region, there is provided one or more voltage-withstanding regions. At least one of the one or more voltage-withstanding regions has a withstand voltage lower than both the withstand voltages of the cell region and the circuit element region.

A semiconductor device according to the present disclosure includes a P layer, an insulating film, an electrode, a plurality of P- layers arranged on a side of a termination region of the P layer, an N- layer, an N++ layer, an insulating film, an electrode, a high permittivity layer disposed at least on the P- layers, and a low permittivity layer disposed on the high permittivity layer, and a distance between an end on a side of an active region of the insulating film and an end on a side of the termination region of one of the P- layers located farthest from the active region is more than .Math.m and .Math.m or less, and a distance between the end on the side of the active region of the insulating film and an end on a side of the active region of the electrode is 50 .Math.m or more.

Power semiconductor devices include a semiconductor layer structure comprising an active area with a plurality of unit cell transistors and an inactive gate pad area, a gate resistor layer on an upper side of the semiconductor layer structure, an inner contact that is directly on the upper side of the gate resistor layer, and an outer contact that is directly on the upper side of the gate resistor layer. The outer contact encloses the inner contact within the inactive gate pad area of the semiconductor device.

A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.

A high-voltage semiconductor device includes a MOS device and a resistor device. The MOS device has a source, a drain, a drain insulation region adjacent to the drain, and a gate adjacent to the source. The resistor device is formed on the drain insulation region and is electrically connected to the drain. The resistor device has a plurality of resistor sections connected in series, and each of the plurality of resistor sections has a curved shape.

High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.

A semiconductor unit includes: a barrier layer including a first compound semiconductor; a channel layer including a second compound semiconductor, and bonded to the barrier layer at a first face; an insulation layer provided on a second face, of the barrier layer, that is on an opposite side of the first face, and having an opening section that exposes the barrier layer; a gate electrode provided to bury the opening section; a source electrode and a drain electrode that are provided on the second face of the barrier layer on both sides of the gate electrode with the gate electrode being interposed; and a material layer including a metal material or a semiconductor material, and provided in contact with the second face of the barrier layer between the gate electrode and the drain electrode.

A semiconductor device including a semiconductor layer, a drain region formed at a surface region of the semiconductor layer, and a source/gate region including a source region and a gate region, which are alternatively arranged so as to be electrically connected to each other. The device further includes a resistive field plate that is disposed on the semiconductor layer between the drain region and the source/gate region and spirally wound in a top view. The field plate including an innermost peripheral portion electrically connected to the drain region and an outermost peripheral portion electrically connected to ground. An outermost peripheral ground conductor film is disposed on the semiconductor layer between the outermost peripheral portion of the field plate and the source/gate region. Additionally, a second ground conductor film is disposed on the semiconductor layer between the outermost peripheral portion of the field plate and the outermost ground conductor film.

A semiconductor device including a low conducting field-controlling element is provided. The device can include a semiconductor including an active region (e.g., a channel), and a set of contacts to the active region. The field-controlling element can be coupled to one or more of the contacts in the set of contacts. The field-controlling element can be formed of a low conducting layer of material and have a lateral resistance that is both larger than an inverse of a minimal operating frequency of the device and smaller than an inverse of a maximum control frequency of the device.