A high power vertical insulated-gate switch is described that includes a parallel cell array having inner cells and an edge cell. The cells have a vertical npnp structure with a trenched field effect device that turns the device on and off. The edge cell is prone to breaking down at high currents. Techniques used to cause the current in the edge cell to be lower than the current in the inner cells, to improve robustness, include: forming a top n-type source region to not extend completely across opposing trenches in areas of the edge cell; forming the edge cell to have a threshold voltage of its field effect device that is greater than the threshold voltage of the field effect devices in the inner cells; and providing a resistive layer between the edge cell and a top cathode electrode electrically contacting the inner cells and the edge cell.

A semiconductor device and a method of manufacturing a semiconductor device capable of suppressing breakdown due to current concentration while suppressing an increase in chip size are provided. According to one embodiment, a semiconductor device has a gate resistance on a main surface side of a semiconductor substrate, a first contact and a second contact connected to an upper surface of the gate resistance, and a carrier discharging portion that discharges the carrier formed in the semiconductor substrate below the gate resistance, the gate resistance having a first contacting portion to which a first contact is connected, a second contacting portion to which a second contact is connected, and a plurality of extending portions with one end connected to the first contacting portion and the other end connected to the second contacting portion. The gate resistance forms an opening between adjacent extending portions and the carrier discharge portion is formed in the opening.

A structure to increase the breakdown voltage of the high electron mobility transistor is provided to solve the problem of function loss under a high voltage state. The structure includes a substrate, a conducting layer located on the substrate, a gate insulating layer and an electric-field-dispersion layer. The upper portion of the conducting layer is an electron supply layer, and the lower portion of the conducting layer is an electron tunnel layer. The gate insulating layer is laminated on the electron supply layer. The electric-field-dispersion layer is laminated on the gate insulating layer. The dielectric constant of the electric-field-dispersion layer is smaller than that of the gate insulating layer. A gate electrode is located between the electric-field-dispersion layer and the gate insulating layer. A source and a drain electrodes are respectively electrically connected to the electric-field-dispersion layer, the gate insulating layer, the electron supply layer, and the electron tunnel layer.

A laterally diffused metal oxide semiconductor device can include: a base layer; a source region and a drain region located in the base layer; a first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; a second conductor at least partially located on the voltage withstanding layer; and a source electrode electrically connected to the source region, where the first and second conductors are spatially isolated, and the source electrode at least covers a space between the first and second conductors.

A semiconductor structure is provided, which includes a semiconductor device, a first conductive layer, and a gate runner. The semiconductor device includes an upper surface, a gate terminal, a source terminal, and a drain terminal. The first conductive layer is deposited on the upper surface and coupled to the source terminal. The gate runner is overlapped with the first conductive layer and coupled to the gate terminal. The gate runner and the first conductive layer are configured to contribute a parasitic capacitance between the gate terminal and the source terminal.

Disclosed is an insulated gate bipolar transistor (IGBT) power device, including a bipolar transistor, a first MOS transistor, a second MOS transistor, a body diode and a body region contact diode. An anode of the body region contact diode and an anode of the body diode are connected to the bipolar transistor. A first gate of the first MOS transistor is externally connected to a gate voltage of the IGBT power device and configured to control turning on and off of the first MOS transistor by means of the gate voltage of the IGBT power device. A second gate of the second MOS transistor is connected to an emitter voltage of the IGBT power device and configured to control turning on and off of the second MOS transistor by means of the emitter voltage of the IGBT power device.

Dielectric super-junction transistors use combinations high dielectric relative permittivity materials and high-mobility materials. An associated electronic device includes a junction portion of a barrier layer adjacent a gate contact and a drain contact. A layered semiconductor device is configured with a junction dielectric permittivity that is greater than a channel dielectric permittivity in the channel layer. The junction portion has a dielectric structure that polarizes carriers within the junction portion such that excess charge on the gate is compensated by an opposite charge in the junction portion of the barrier layer proximate the gate. A sheet charge in the barrier layer is increased to form a depletion region with the channel layer that avoids a conductive parallel channel in the barrier layer to the drain contact.

According to one embodiment, a semiconductor device includes first, second, and third electrodes, first, second, and third semiconductor regions, a first member, and a first insulating member. A direction from the first electrode toward the second electrode is along a first direction. The first semiconductor region includes first, second, and third partial regions. A second direction from the second partial region toward the first partial region crosses the first direction. The third partial region is between the second partial region and the second semiconductor region in the first direction. The third semiconductor region is provided between the third partial region and the second semiconductor region. The first insulating member includes a first insulating region and a second insulating region. The first insulating region is between the third partial region and the first member. The second insulating region is between the third semiconductor region and the third electrode.

Some embodiments relate to an integrated circuit. The integrated circuit includes a ring-shaped drain region having an inner edge and an outer edge. A channel region surrounds the ring-shaped drain region. A source region surrounds the channel region. The channel region separates the drain region from the source region. A gate electrode is arranged over the channel region and is separated from the channel region by a gate dielectric. An inner edge of the gate electrode is proximate to the drain region. A resistor structure is arranged over and spaced apart from an upper surface of the substrate. The resistor structure has a first end and a second end which are connected by a curved or polygonal path of resistive material. The first end is coupled to the ring-shaped drain. The resistor has an outer perimeter that is surrounded by the inner edge of the ring-shaped drain region.

A semiconductor device that allows easy hole extraction is provided. The semiconductor device includes: a semiconductor substrate having drift and base regions; a transistor portion formed in the semiconductor substrate; and a diode portion formed adjacent to the transistor portion and in the semiconductor substrate. In the transistor portion and the diode portion: a plurality of trench portions each arrayed along a predetermined array direction; and a plurality of mesa portions formed between respective trench portions are formed, among the plurality of mesa portions, at least one boundary mesa portion at a boundary between the transistor portion and the diode portion includes a contact region at an upper surface of the semiconductor substrate and having a concentration higher than that of the base region, and an area of the contact region at the boundary mesa portion is greater than an area of the contact region at another mesa portion.