The application relates to a semiconductor die having a semiconductor body including an active region, an insulation layer on the semiconductor body, and a sodium stopper formed in the insulation layer. The sodium stopper is arranged in an insulation layer groove which intersects the insulation layer vertically and extends around the active region. The sodium stopper is formed of a tungsten material filling the insulation layer groove.

The present invention introduces a new shielded gate trench MOSFETs wherein epitaxial layer having special multiple stepped epitaxial (MSE) layers with different doping concentrations decreasing in a direction from substrate to body regions, wherein each of the MSE layers has uniform doping concentration as grown. Specific on-resistance is significantly reduced with the special MSE structure. Moreover, in sore preferred embodiment, an MSO (multiple stepped oxide) structure is applied to the shielded gate structure to further reduce the specific on-resistance and enhance device ruggedness.

Provided is a semiconductor device including: a drift region of first conductivity type provided in a semiconductor substrate; a base region of second conductivity type provided in the semiconductor substrate; an emitter region of first conductivity type provided at a front surface of the semiconductor substrate; a contact region of second conductivity type provided on the base region and having a higher doping concentration than the base region; a contact trench portion provided at the front surface of the semiconductor substrate; a first barrier layer provided at a side wall and a bottom surface of the contact trench portion; and a second barrier layer provided in contact with the contact region at the side wall of the contact trench portion.

A semiconductor device includes; a semiconductor substrate; an emitter electrode provided on the semiconductor substrate; a gate electrode provided on the semiconductor substrate; a drift layer of a first conduction type provided in the semiconductor substrate; a source layer of the first conduction type provided on an upper surface side of the semiconductor substrate; a base layer of a second conduction type provided on the upper surface side of the semiconductor substrate; a collector electrode provided below the semiconductor substrate; and a two-part dummy active trench including, at an upper part, an upper dummy part not connected with the gate electrode and including, at a lower part, a lower active part connected with the gate electrode and covered by an insulating film, in a trench of the semiconductor substrate, wherein a longitudinal length of the lower active part is larger than a width of the lower active part.

There is provided a semiconductor device comprising: a semiconductor substrate including a drift region of a first conductivity type; an emitter region of the first conductivity type provided above the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a base region of a second conductivity type provided between the emitter region and the drift region inside the semiconductor substrate; a first accumulation region of the first conductivity type provided between the base region and the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a plurality of trench portions provided to pass through the emitter region, the base region and first accumulation region from an upper surface of the semiconductor substrate, and provided with a conductive portion inside; and a capacitance addition portion provided below the first accumulation region to add a gate-collector capacitance thereto.

A semiconductor device includes a semiconductor layer with a thickness of at most 50 μm. A first metallization structure is disposed on a first surface of the semiconductor layer. The first metallization structure includes a first copper region with a first thickness. A second metallization structure is disposed on a second surface of the semiconductor layer opposite to the first surface. The second metallization structure includes a second copper region with a second thickness.

A semiconductor device includes a semiconductor substrate, a transistor section, a diode section, and a boundary section provided between the transistor section and the diode section in the semiconductor substrate. The transistor section has gate trench portions which are provided from an upper surface of the semiconductor substrate to a position deeper than that of an emitter region, and to each of which a gate potential is applied. An upper-surface-side lifetime reduction region is provided on the upper surface side of the semiconductor substrate in the diode section and a partial region of the boundary section, and is not provided in a region that is overlapped with the gate trench portion in the transistor section in a surface parallel to the upper surface of the semiconductor substrate.

The disclosure provides a superjunction IGBT (insulated gate bipolar transistor) device, wherein a carrier storage layer of a first conductivity type is provided between a voltage sustaining layer and a base region, and a MISFET (metal-insulator-semiconductor field effect transistor) of a second conductivity type is also integrated in a cell, with at least one gate of the MISFET is connected to the emitter contact thereof. The MISFET is turned off at a low forward conduction voltage, helping to reduce the conduction voltage drop. The MISFET can provide a path for carriers of a second conductivity type and prevent the carrier storage layer from suffering a high electric field when the forward conduction voltage is slightly higher or it is at the forward blocking state, helping to improve the reliability.

Power semiconductor device capable of controlling slope of current and voltage during dynamic switching disclosed. The power semiconductor device may include a semiconductor substrate and a cell array being consisted of a plurality of transistor cells on an active area, wherein each of the plurality of transistor cells may include an emitter region, a body region, a contact region and a gate region, wherein non-uniform threshold voltages may be respectively set in the plurality of transistor cells constituting the cell array, wherein a gate signal may be applied to each of the plurality of transistor cells through an input/output unit, wherein the input/output unit may include a first gate signal path configured for supplying a gate charging current to the gate regions in each of the plurality of transistor cells and a second gate signal path configured for discharging a gate discharging current from the gate region.

A shielded gate MOSFET device and a manufacturing method thereof is provided. In the method, the shielded gate thick dielectric layers are formed with the thick oxide layer process at the bottoms in the trenches, poly is deposited in each trench and is back etched to leave gate poly on the side wall of each trench, whereas the portion, right in the center of each trench, of the thin poly layer is removed to be filled with the contact hole dielectric layer, which achieves the effect of streamlining the process flow.