The present invention introduces a new shielded gate trench SBR (Super Barrier Rectifier) wherein an epitaxial layer having special MSE (multiple stepped epitaxial) layers with different doping concentrations decreasing in a direction from a substrate to a top surface of the epitaxial layer, wherein each of the MSE layers has an uniform doping concentration as grown. Forward voltage V.sub.f is significantly reduced with the special MSE layers. An integrated circuit comprising a SGT MOSFET and a SBR formed on a single chip obtains benefits of low on-resistance, low reverse recovery time and high avalanche capability from the special MSE layers.

A semiconductor device includes: a semiconductor layer; a gate trench formed in the semiconductor layer; an insulating layer formed on the semiconductor layer; a gate electrode buried in the gate trench via the insulating layer; a gate wiring formed on the insulating layer and electrically connected to the gate electrode; and a protection trench formed in the semiconductor layer, wherein the semiconductor layer includes an outer peripheral region including outer edges of the semiconductor layer in a plan view and an inner region surrounded by the outer peripheral region, wherein the gate trench includes an outer peripheral gate trench portion arranged in the outer peripheral region and surrounded by the protection trench in a plan view, and wherein the outer peripheral gate trench portion and the protection trench are formed in a closed annular shape along the outer edges of the semiconductor layer in the outer peripheral region.

A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type formed on the semiconductor substrate and having a first conductivity type impurity concentration higher than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type formed above the first semiconductor layer, a first device region formed in the second semiconductor layer and configured to operate based on a first reference voltage, a second device region formed in the second semiconductor layer and configured to operate based on a second reference voltage, the second device region being spaced apart from the first device region, and a region isolation structure interposed between the first and second device regions and formed in a region extending from a front surface of the second semiconductor layer to the first semiconductor layer so as to electrically isolate the first and second device regions from each other.

First dopants are implanted through a larger opening of a first process mask into a silicon carbide body, wherein the larger opening exposes a first surface section of the silicon carbide body. A trench is formed in the silicon carbide body in a second surface section exposed by a smaller opening in a second process mask. The second surface section is a sub-section of the first surface section. The larger opening and the smaller opening are formed self-aligned to each other. At least part of the implanted first dopants form at least one compensation layer portion extending parallel to a trench sidewall.

According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.

Provided are a semiconductor device in which the lifetime of holes is controlled and the switching loss is suppressed, and a method of manufacturing the same. Provided are a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface, a first buffer layer of the first conductive type provided between the drift layer and the second main surface in contact with the drift layer, having a resistivity lower than that of the drift layer, and having an impurity concentration higher than that of the drift layer, and a high resistivity layer provided between the first buffer layer and the second main surface and having a resistivity higher than that of the drift layer.

In a semiconductor device according to the technology disclosed in the present specification, a temperature detection region is provided with a diffusion layer of a second conductivity type provided on a surface layer of a drift layer of a first conductivity type, a well layer of a first conductivity type provided on a surface layer of the diffusion layer and electrically connected to an anode electrode, and a cathode layer of a first conductivity type provided on a surface layer of the well layer and electrically connected to a cathode electrode.

According to one embodiment, a semiconductor device includes first to third electrodes, a first wiring member, a semiconductor member, and an insulating member. The first wiring member includes a first extending portion. A part of the third electrode is between the first electrode and the first extending portion. An other part of the third electrode is between the first and second electrodes. The semiconductor member is provided between the first and second electrodes and between the first electrode and the first extending portion. The semiconductor member includes first to sixth semiconductor regions. The first semiconductor region includes first and second partial regions. The first partial region is located between the first electrode and the third electrode. The insulating member includes the first insulating region. The first insulating region is provided between the third electrode and the semiconductor member.

In an embodiment, a method of forming a field plate in an elongate active trench of a transistor device is provided. The elongate active trench includes a first insulating material lining the elongate active trench and surrounding a gap and first conductive material filling the gap. The method includes selectively removing a first portion of the first insulating material using a first etch process, selectively removing a portion of the first conductive material using a second etch process, and forming a field plate in a lower portion of the elongate active trench and selectively removing a second portion of the first insulating material using a third etch process. The first etch process is carried out before the second etch process and the second etch process is carried out before the third etch process.

A semiconductor device includes a semiconductor substrate, a contact region, a carrier suppression region and an electrode. The semiconductor substrate is shared by an insulated gate bipolar transistor (IGBT) region with an IGBT element and a freewheeling diode (FWD) region with an FWD element. The carrier suppression region is exposed from a surface of the semiconductor substrate in the IGBT region, and has a lower impurity concentration than the contact region. The carrier suppression region has a Schottky barrier junction with the electrode.