Provided is a carbon nanotube (CNT) network which can improve an electrical joint so that a sufficient amount of current flows into a thin film and the amount of current is controlled. A network of CNT or a CNT hybrid material is constructed by distributing, as a node between CNT and CNT in a CNT thin film, a fine particle of an inorganic semiconductor and preferably fine particles of a metal halide, a metal oxide, or a metal sulfide.

An electronic device is disclosed. The electronic device includes: a first electrode disposed on a substrate and extending in a first direction; a second electrode disposed above the first electrode and extending in a second direction intersecting the first direction; and at least one switching particle disposed between the first electrode and the second electrode and bonded to the first electrode and the second electrode via van der Waals bond, wherein the switching particle controls flow of current between the first electrode and the second electrode, based on a difference of voltages of the first electrode and the second electrode applied thereto.

A nanosheet semiconductor device and fabrication method are described for integrating the fabrication of nanosheet transistors (71) and capacitors/sensors (72) in a single nanosheet process flow by forming separate transistor and capacitor/sensor stacks (12A-16A, 12B-16B) which are selectively processed to form gate electrode structures (68A-C) which replace remnant SiGe sandwich layers in the transistor stack, to form silicon fixed electrodes using silicon nanosheets (13C, 15C) on a first side of the capacitor/sensor stack, and to form SiGe fixed electrodes using SiGe nanosheets (12C, 14C, 16C) from the middle of remnant SiGe sandwich layers in the capacitor/sensor stack (e.g., 16-2) which are separated from the silicon fixed electrodes by selectively removing top and bottom SiGe nanosheets (e.g., 16-1, 16-3) from the remnant SiGe sandwich layers in the capacitor/sensor stack.

The present disclosure relates to a semiconductor device comprising a first electrode, a second electrode, a third electrode, a fourth electrode, an insulating layer, and a nano-heterostructure. The nano-heterostructure comprises a first surface and a second surface. The first metallic carbon nanotube is located on the first surface and extends in a first direction. The semiconducting carbon nanotube is located on the first surface and extends in the first direction. The semiconducting carbon nanotube is parallel and spaced away from the first metallic carbon nanotube. The second metallic carbon nanotube is located on the second surface and extends in a second direction. An angle forms between the first direction and the second direction.

A semiconductor nanowire device includes at least one semiconductor nanowire having a bottom surface and a top surface, an insulating material which surrounds the semiconductor nanowire, and an electrode ohmically contacting the top surface of the semiconductor nanowire. A contact of the electrode to the semiconductor material of the semiconductor nanowire is dominated by the contact to the top surface of the semiconductor nanowire.

A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

Techniques for selective CD shrink for source and drain contact trench to optimize FET device performance are provided. In one aspect, a semiconductor FET device includes: at least one gate; source and drains on opposite sides of the at least one gate; recesses in the source and drains; and metal contacts disposed over the source and drains and in the recesses, wherein the metal contacts are in direct contact with a bottom and sidewalls of each of the recesses in both a first direction and a second direction, wherein the first direction is perpendicular to the at least one gate, and wherein the second direction is parallel to the at least one gate. A method of forming a semiconductor FET device is also provided.

A transistor includes a first gate structure, a channel layer, and source/drain contacts. The first gate structure includes nanosheets. The channel layer is over the first gate structure. A portion of the channel layer wraps around the nanosheets of the first gate structure. The source/drain contacts are aside the nanosheets. The source/drain contacts are electrically connected to the channel layer.

Disclosed are an oxide semiconductor thin film transistor and a method of fabricating the same. An oxide semiconductor thin film transistor according to an embodiment of the present disclosure includes a substrate; a first gate electrode formed on the substrate; a gate insulator formed on the first gate electrode; an oxide semiconductor layer formed on the gate insulator; source and drain electrodes formed by depositing carbon nanotubes (CNTs) and a metal electrode on the formed the oxide semiconductor layer and patterning the deposited CNTs and metal electrode such that the source electrode and the drain electrode are spaced apart from each other; and a passivation layer formed on the formed source and drain electrodes, wherein the source and drain electrodes serve to prevent diffusion of a metal of the metal electrode into the formed oxide semiconductor layer, due to the CNTs of the source and drain electrodes.

A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.