Embodiments of the present invention provide a conductive substrate, a manufacturing method thereof and a display device. The conductive substrate includes a base substrate and a first conductive layer and a second conductive layer disposed on the base substrate, wherein the first conductive layer and the second conductive layer contact with each other, the first conductive layer is configured to be electrically connected with separated parts after the second conductive layer is fractured, and the first conductive layer includes a composite material layer or a nanowire conductive network layer.

According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

Composite transparent conductors are described, which comprise a primary conductive medium based on metal nanowires and a secondary conductive medium based on a continuous conductive film.

A device includes a gate electrode and a gate dielectric surrounding the gate electrode. The gate electrode surrounds a nanostructure. The nanostructure includes stacked nanosheets. The gate dielectric is formed by a high-k (HK) material. The HK material covers sidewalls of the gate electrode in a direction aligned to adjacent devices. Portions of the HK material are recessed from the sidewalls and refilled by a dielectric material with a dielectric constant less than the HK material and an electrical isolation capability greater than the HK material. Replacing the HK material over the sidewalls of the gate electrode with the dielectric material enhances electrical isolation between the gate electrode with adjacent contacts. Consequently, it can reduce electrical leakage between metal gate (MG) contacts and metal-to-device (MD) contacts in scaled transistors of an integrated circuit (IC).

Contact over active gate (COAG) structures with uniform and conformal gate insulating cap layers, and methods of fabricating contact over active gate (COAG) structures using uniform and conformal gate insulating cap layers, are described. In an example, an integrated circuit structure includes a gate structure. An epitaxial source or drain structure is laterally spaced apart from the gate structure. A dielectric spacer is laterally between the gate structure and the epitaxial source or drain structure, the dielectric spacer having an uppermost surface below an uppermost surface of the gate structure. A gate insulating cap layer is on the uppermost surface of the gate structure and along upper portions of sides of the gate structure, the gate insulating cap layer distinct from the dielectric spacer.

A field effect transistor includes a substrate, a material layer on a surface of the substrate and including a two-dimensional material or carbon nanotubes, and particles interposed between the substrate and the material layer.

Provided are two-dimensional material (2D)-based wiring conductive layer contact structures, electronic devices including the same, and methods of manufacturing the electronic devices. A 2D material-based field effect transistor includes a substrate; first to third 2D material layers on the substrate; an insulating layer on the first 2D material layer; a source electrode on the second 2D material layer; a drain electrode on the third 2D material layer; and a gate electrode on the insulating layer. The first 2D material layer is configured to exhibit semiconductor characteristics, and the second and third 2D material layers are metallic 2D material layers. The first 2D material layer may include a first channel layer of a 2D material and a second channel layer of a 2D material. The first 2D material layer may partially overlap the second and third 2D material layers.

Interconnects may be formed to an electronic device by creating a strong bond between a wire or lead, one or more nanomaterials, and a contacting area on the electronic device. The creating of the strong bond comprises triggering low power air plasma to activate a surface of the one or more nanomaterials forcing the one or more nanomaterials to bond to the surface of the contacting area.

A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.

The present invention pro ides a method of providing an electrical contact on a graphene surface, the method comprising: (i) providing a graphene layer structure comprising one or more graphene layers and having a polymer coating on a surface thereof; (ii) contacting one or more portions of the polymer coating with a conductive metal-containing composition comprising a solvent, wherein the polymer coating is soluble in the solvent: and (iii) volatilising the solvent to deposit the conductive metal on the surface of the graphene layer structure.