According to example embodiments, an integrated circuit includes a continuous active region extending in a first direction, a tie gate electrode extending in a second direction crossing the first direction on the continuous active region, a source/drain region provided adjacent the tie gate electrode, a tie gate contact extending in a third direction perpendicular to the first direction and the second direction on the continuous active region and connected to the tie gate electrode, a source/drain contact extending in the third direction and connected to the source/drain region, and a wiring pattern connected to each of the tie gate contact and the source/drain contact and extending in a horizontal direction. A positive supply power is applied to the wiring pattern.

Disclosed are a semiconductor device and a method of fabricating the same. The device includes an FEOL layer, which includes a plurality of individual devices, on a substrate, and first, second, and third metal layers sequentially stacked on the FEOL layer. The second metal layer includes an interlayer insulating layer and an interconnection line in the interlayer insulating layer. The interconnection line includes a lower via portion electrically connected to the first metal layer, an upper via portion electrically connected to the third metal layer, and a line portion between the lower via portion and the upper via portion. A line width of an upper portion of the interconnection line gradually decreases in a vertical direction away from the substrate, and a line width of a lower portion of the interconnection line gradually increases in a vertical direction away from the substrate.

According to one embodiment, a semiconductor device includes first, second, third nitride members, first, second, third electrodes, and a first insulating member. The first nitride member includes a first face along a first plane, a second face along the first plane, and a third face. The third face is connected with the first and second faces between the first and second faces. The third face crosses the first plane. The first face overlaps a part of the first nitride member. The second nitride member includes a first nitride region provided at the first face. The third nitride member includes a first nitride portion provided at the second face. The first electrode includes a first connecting portion. The second electrode includes a second connecting portion. The third electrode includes a first electrode portion. The first insulating member includes a first insulating region.

Techniques for recovering the width of a top gate spacer in a field-effect transistor (FET) device are provided. In one aspect, a FET device includes: at least one gate; source/drain regions present on opposite sides of the at least one gate; gate spacers offsetting the at least one gate from the source/drain regions, wherein each of the gate spacers includes an L-shaped spacer alongside the at least one gate and a dielectric liner disposed on the L-shaped spacer; and at least one channel interconnecting the source/drain regions. A method of forming a FET device is also provided which includes recovering the width of the top gate spacer using the dielectric liner.

Embodiments of the present disclosure provide a FinFET. The FinFET may include fin-type active regions protruding from a substrate, the fin-type active regions extending in a first direction, a field insulating layer on a surface of the substrate between the fin-type active regions, and gate structures disposed on surfaces of the fin-type active regions and a surface of the field insulating layer, the gate structures extending in a second direction perpendicular to the first direction. Each of the gate structures may include a gate dielectric layer conformally disposed on the surfaces of the fin-type regions and a gate electrode on the gate dielectric layer. The gate electrode may include low concentration impurity regions close to the field insulating layer, and high concentration impurity regions close to an upper portion of the fin-type active regions.

A semiconductor device includes a plurality of column portions made of a semiconductor. The plurality of column portions each include a source region, a drain region, and a channel formation region including a channel formed between the source region and the drain region. The semiconductor device further includes: a gate electrode provided at a side wall of the channel formation region with an insulating layer being interposed between the gate electrode and the side wall; a first semiconductor layer coupled to either one of the source region and the drain region of each of the plurality of column portions; and a first metal layer coupled to the first semiconductor layer.

A vertical semiconductor transistor is provided that includes: a source region, a drain region, and a body region formed in a semiconductor substrate; wherein the source region and the drain region are doped with a first type dopant; wherein the body region is doped with a second type dopant; and wherein the second type dopant has a doping profile within the body region that varies with distance from the source region.

A transistor including a gate region penetrating into a first gallium nitride layer, wherein a second electrically-conductive layer coats at least one of the sides of said gate region.

A transistor including a gate region penetrating into a first gallium nitride layer, wherein a second electrically-conductive layer coats at least one of the sides of said gate region.

A vertical field-effect transistor includes a substrate comprising a semiconductor material; a first set of fins formed from the semiconductor material and extending vertically with respect to the substrate; and a second set of fins extending vertically with respect to the substrate, wherein ones of the second set of fins abut ones of the first set of fins. The second set of fins comprises a dielectric material.